參數(shù)資料
型號(hào)： SLA24C64-S
廠商： SIEMENS A G
元件分類(lèi)： DRAM
英文描述： 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述： 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： PLASTIC, DSO-8
文件頁(yè)數(shù)： 16/26頁(yè)
文件大小： 358K
代理商： SLA24C64-S
SLx 24C64
Semiconductor Group
16
Preliminary 1998-07-27
6.2
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Current Address Read
Figure 12
Current Address Read
Transmission of CSR
For a current address read the master generates a START
condition, which is followed by the command byte CSR (Chip
Select Read). The receipt of the CSR-byte is acknowledged by
the EEPROM with a low on the SDA line.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Transmission of
EEPROM Data
STOP Condition from
Master
Command Byte
CSR
S
P
A
C
K
S
T
A
R
T
T
O
P
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02132
Data Byte
1
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