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參數(shù)資料
| 型號： | SLA 24C64 |
| 廠商： | SIEMENS AG |
| 元件分類： | DRAM |
| 英文描述： | 64 Kbit (8192 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(64K位 (8192 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制)) |
| 中文描述： | 64千位（8192 × 8位）串行的CMOS EEPROM，帶有國際進(jìn)口同步2線巴士（64K的位（8192 × 8位）串行的CMOS EEPROM的（帶有國際進(jìn)口同步2線控制）） |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | SLA 24C64 |
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SLx 24C64
Semiconductor Group
13
1999-02-02
5
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one
programming procedure. Setting the Write Protection pin WP to
V
CC
activates the
hardware write protection and therefore any programming is suppressed. For normal
operation WP has to be set to
V
SS
.
Write Operations
5.1
Byte Write
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3
, Acknowledge Polling for further information.
Address Setting
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following two bytes AHI/ALO
with the EEPROM address (A0 to A12) are loaded into the
address counter of the EEPROM and acknowledged by the
EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the bytes AHI (A8 to A12)
and ALO (A0 to A7). The programming procedure consists of
an internally timed erase/write cycle. In the first step, the
selected byte is erased to
“1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
Transmission of Data
Programming Cycle
Command Byte
CSW
S
P
C
K
A
C
K
A
S
T
A
R
T
T
O
P
S
EEPROM Address
AHI
Data Byte
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02518
C
K
A
0
EEPROM Address
ALO
C
K
A
相關(guān)PDF資料 |
PDF描述 |
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| SLE 24C64 | 64 Kbit (8192 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(64K位 (8192 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制)) |
| SLA24C164-D | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLE24C164-D | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLE24C164-S | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C164-S | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SLA24C64-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C64-D/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C64-D-3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C64-D-3/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C64-S | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
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