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參數(shù)資料
| 型號(hào)： | SLA 24C164 |
| 廠商： | SIEMENS AG |
| 元件分類： | DRAM |
| 英文描述： | 16 Kbit (2048 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(16K位 (2048 × 8 位) CMOS串行EEPROM(帶IIC控制)) |
| 中文描述： | 16千位（2048 × 8位）串行的CMOS EEPROM，帶有國(guó)際進(jìn)口同步2線巴士（16K的位（2048 × 8位）的CMOS串行EEPROM的（帶控制國(guó)際進(jìn)口許可證）） |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | SLA 24C164 |
SLx 24C164
Semiconductor Group
14
1999-02-02
5.2
Page Write
Those bytes of the page that have not been addressed are not included in the
programming.
Figure 8
Page Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3
Acknowledge Polling).
Address Setting
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum sixteen data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by EEA (A0 to A7) and CSW (A8 to
A10). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A4 through A10.
Only the respective four least significant address bits A0
through A3 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to
“1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Transmission of Data
Programming Cycle
Command Byte
CSW
S
P
C
K
A
S
T
A
R
T
T
O
P
S
EEPROM Address
EEA n
Data Byte n
Data Byte n+1
Data Byte n+15
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02140
0
C
K
A
C
K
A
C
K
A
C
K
A
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PDF描述 |
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| SLE 24C164 | 16 Kbit (2048 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(16K位 (2048 × 8 位) CMOS串行EEPROM(帶IIC控制)) |
| SLA 24C32 | 32 Kbit (4096 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(32K位(4096 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制)) |
| SLE 24C32 | 32 Kbit (4096 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(32K位(4096 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制)) |
| SLA 24C64 | 64 Kbit (8192 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(64K位 (8192 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SLA24C164-D | 制造商:Siemens 功能描述:2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| SLA24C164-D/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
| SLA24C164-D-3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C164-D-3/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
| SLA24C164-S | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
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