參數(shù)資料
型號(hào): SLA 24C08
廠商: SIEMENS AG
元件分類: DRAM
英文描述: 8Kbit (1024 × 8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(8K位 (1024 × 8 位) CMOS串行EEPROM(帶IIC控制))
中文描述: 8Kbit(1024 × 8位)串行的CMOS EEPROM,帶有國(guó)際進(jìn)口同步2線巴士(8K的位(1024 × 8位)的CMOS串行EEPROM的(帶控制國(guó)際進(jìn)口許可證))
文件頁數(shù): 14/23頁
文件大?。?/td> 323K
代理商: SLA 24C08
SLx 24C08/16
Semiconductor Group
14
1999-02-02
6.3
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue (see
figure 10
).
Acknowledge Polling
Figure 9
Flow Chart “Acknowledge Polling”
Internal Programming
Procedure
Send Start
Send CS-Byte
from EEPROM
received
Acknowledge
Next Operation
No
Yes
IED02131
相關(guān)PDF資料
PDF描述
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SLA 24C32 32 Kbit (4096 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(32K位(4096 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制))
SLE 24C32 32 Kbit (4096 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(32K位(4096 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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