參數(shù)資料
型號(hào): SL28647CLCT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 24/27頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK CK505 DIFF PAIR 72QFN
標(biāo)準(zhǔn)包裝: 2,000
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:22
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28647
.......................Document #: 001-05103 Rev *B Page 6 of 27
Byte 2 Control Register 2
Bit
@Pup
Name
Description
7
1
PCIF0_OE
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
27M_non_SS/DOT_96_OE 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable, 1 = Enabled
5
1
48M_OE
48-MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF0_OE
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
1
REF1_OE
REF1 Output Enable
0 = Disabled, 1 = Enabled
2
1
CPU1_OE
CPU[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
1
CPU0_OE
CPU[T/C]0 Output Enable
0 = Disabled, 1 = Enabled
0
1
CPU, SRC, PCI, PCIF
Spread Enable
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 3 Control Register 3
Bit
@Pup
Name
Description
7
1
PCI4_OE
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI3_OE
PCI3 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI2_OE
PCI2 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI1_OE
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
1
RESERVED
2
1
RESERVED
1
CPU2/SRC10_OE
CPU2/SRC10 Output Enable
0 = Disabled, 1 = Enabled
0
1
RESERVED
Byte 4 Control Register 4
Bit
@Pup
Name
Description
7
0
SRC7_STP_CTRL
Allow control of SRC7 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC6_STP_CTRL
Allow control of SRC6 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC5_STP_CTRL
Allow control of SRC5 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC4_STP_CTRL
Allow control of SRC4 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3_STP_CTRL
Allow control of SRC3 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2_STP_CTRL
Allow control of SRC2 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1_STP_CTRL
Allow control of SRC1 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
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