參數(shù)資料
型號: SI5369D-C-GQR
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
封裝: 14 X 14 MM, ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù): 84/84頁
文件大?。?/td> 870K
代理商: SI5369D-C-GQR
Preliminary Rev. 0.4
9
3-Level Input Pins4
Input Voltage Low
VILL
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x
VDD
—0.55 x VDD
V
Input Voltage High
VIHH
0.85 x
VDD
——
V
Input Low Current
IILL
See Note 4
–20
A
Input Mid Current
IIMM
See Note 4
–2
+2
A
Input High Current
IIHH
See Note 4
20
A
LVCMOS Output Pins
Output Voltage Low
VOL
IO = 2 mA
VDD =1.71V
——
0.4
V
Output Voltage Low
IO = 2 mA
VDD =2.97V
——
0.4
V
Output Voltage High
VOH
IO = –2 mA
VDD =1.71V
VDD
0.4
——
V
Output Voltage High
IO = –2 mA
VDD =2.97V
VDD
0.4
——
V
Disabled Leakage
Current
IOZ
RSTb = 0
–100
100
A
Table 3. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1.
Current draw is independent of supply voltage
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD ≥ 2.5 V.
4.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6.
The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
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