- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9029 > SI5350C-A-GU (Silicon Laboratories Inc)IC CLK GEN PLL BLANK CUST 24QSOP PDF資料下載
參數(shù)資料
| 型號： | SI5350C-A-GU |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 24QSOP |
| 標準包裝： | 56 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:8 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 管件 |
Si5350C
Rev. 0.9
13
Up to two frequency select pins are available on the Si5350C. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible.
The Si5350C uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
4.4.3. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Similar to the FS pins, each OEB pin
can be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0,
CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4,
and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the
pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Figure 9. Example Configuration of a Pin-Controlled Output Enable
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS_0
FS_1
FS_0
0
1
F1_0, F1_3, F1_5
F2_0, F2_3, F2_5
Output Frequency
FS_1
0
1
F1_1, F1_2, F1_4
Output Frequency
CLKx
Frequency_A
Frequency_B
Full cycle completes before
changing to a new frequency
Frequency_A
New frequency starts
at its leading edge
Glitchless Frequency Changes
Cannot be controlled
by FS pins
Customizable FS Control
F2_1, F2_2, F2_4
MultiSynth 0
FS
MultiSynth 1
FS
MultiSynth 2
FS
MultiSynth 3
FS
MultiSynth 4
FS
MultiSynth 5
FS
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
OEB_0
OEB_1
OEB_0
0
1
CLK Enabled
CLK Disabled
Output State
OEB_2
OEB_1
0
1
CLK Enabled
CLK Disabled
Output State
OEB_2
0
1
CLK Enabled
CLK Disabled
Output State
Clock continues until
cycle is complete
CLKx
OEBx
Clock starts on the
first leading edge
Glitchless Output Enable
Customizable OEB Control
OEB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| D38999/24WG11PB | CONN RCPT 11POS JAM NUT W/PINS |
| VE-23D-MW-F1 | CONVERTER MOD DC/DC 85V 100W |
| VI-24R-MY-F1 | CONVERTER MOD DC/DC 7.5V 50W |
| VE-J71-MZ-F3 | CONVERTER MOD DC/DC 12V 25W |
| SI5350B-A-GU | IC CLK GEN PLL BLANK CUST 24QSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5350C-A-GUR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Dual PLL 133MHz Clk Dual In 8 Outs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350C-Axxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with Dual Input, 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350C-Axxxxx-GT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with Dual Input, 3 outputs, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350C-Axxxxx-GU | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with Dual Input, 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5350C-B02166-GT | 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。