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參數(shù)資料
| 型號： | SI5334C-A00120-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 11/34頁 |
| 文件大?。?/td> | 233K |
| 代理商： | SI5334C-A00120-GMR |
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Si5334
Preliminary Rev. 0.16
19
3IN3
I
Multi
Keep the input level > –0.1 V and < VDD+.1 V.
REFCLKSE
High impedance input for single-ended clock signals
such as CMOS. The input should be dc-coupled.
PINC
This pin function is active for devices Si5334D/E/F. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will increase the input to output device
latency by a factory-programmed amount. The function
of this pin is factory programmed.
FINC
This pin function is active for devices Si5334G/H/J. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will increase the output frequency of the
clock output by a factory-programmed amount. The
function of this pin is factory-programmed.
If this pin is unused, it should be grounded.
4IN4
I
LVCMOS
Keep the input level > –0.1 V and < VDD+ 0.1 V.
FDBKSE
High Impedance input for single-ended clock signals,
such as CMOS, when the zero delay mode of operation
is required. This input should be dc-coupled.
PDEC
This pin function is active for devices Si5334D/E/F. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will decrease the input to output device
latency by a factory-programmed amount. The function
of this pin is factory-programmed.
FDEC
This pin function is active for devices Si5334G/H/J. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will decrease the output frequency of the
clock output by a factory-programmed amount. The
function of this pin is factory-programmed.
If this pin is unused, it should be grounded.
5,6
IN5/IN6
I
Multi
FDBK/FDBKB
These pins form a differential input for feedback clock
signals when a zero delay mode of operation is in effect.
Always AC couple into these pins. When not is use
leave FDBK unconnected and connect FDBK to ground.
7
VDD
Supply
Core Supply Voltage
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 F bypass capacitor should be located very close to
this pin.
Table 15. Si5334 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5334C--A00104-GM | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00112-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00114-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334B-A00156-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00125-GM | PLL BASED CLOCK DRIVER, QCC24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5334C-A00126-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00126-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00128-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00128-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00130-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
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