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參數(shù)資料
| 型號： | SI5334C-A00107-GM |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 3/34頁 |
| 文件大?。?/td> | 233K |
| 代理商： | SI5334C-A00107-GM |
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Si5334
Preliminary Rev. 0.16
11
PCI Express 3.0
Random Jitter
(12kHz—20MHz)3
JPCIERJ2
CLKIN = 25 MHz
All CLKn at 100 MHz
Spread Spectrum not
enabled4
—
0.7
1
ps RMS
PCI Express 3.0
Period Jitter
CLKIN = 25 MHz
All CLKn at 100 MHz
Spread Spectrum not
enabled4
—8
15
ps pk-pk
PCI Express 3.0
Cycle-Cycle Jitter
CLKIN = 25 MHz
All CLKn at 100 MHz
Spread Spectrum not
enabled4
—
13
30
ps pk-pk
Period Jitter
JPER
N = 10,000 cycles5
—
10
30
ps pk-pk
Cycle-Cycle Jitter
JCC
N = 10,000 cycles
Output MultiSynth
operated in integer or
fractional mode5
—
9
29
ps pk6
Random Jitter
(12kHz–20MHz)
RJ
Output and feedback
MultiSynth in integer or
fractional mode5
—
0.7
1.5
ps RMS
Deterministic Jitter
DJ
Output MultiSynth
operated in fractional
mode5
—3
15
ps pk-pk
Output MultiSynth
operated in integer
mode5
—2
10
ps pk-pk
Total Jitter
(12kHz–20MHz)
TJ =DJ+14xRJ
(See Note 7)
Output MultiSynth
operated in fractional
mode5
—
13
36
ps pk-pk
Output MultiSynth
operated in integer
mode5
—
12
20
ps pk-pk
Table 12. Jitter Specifications1,2 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. DJ for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
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PDF描述 |
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| SI5334C-A00140-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334B-A00109-GM | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334B-A00121-GMR | PLL BASED CLOCK DRIVER, QCC24 |
| SI5334C-A00115-GM | PLL BASED CLOCK DRIVER, QCC24 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5334C-A00112-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00112-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00115-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00115-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00116-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
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