參數(shù)資料
型號(hào): SI5334C-A00099-GM
廠商: SILICON LABORATORIES
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁(yè)數(shù): 31/34頁(yè)
文件大?。?/td> 233K
代理商: SI5334C-A00099-GM
Si5334
6
Preliminary Rev. 0.16
MultiSynth Frequency
Synthesis Resolution
fRES
Output frequency < Fvco/8
0
1
ppb
CLKIN Loss of Signal Assert
Time
tLOS
—2.6
5
s
CLKIN Loss of Signal De-assert
Time
tLOS_b
0.01
0.2
1
s
PLL Loss of Lock Detect Time
tLOL
—5
10
ms
POR to Output Clock Valid
tRDY
——
2
ms
Input-to-Output Propagation
Delay
tPROP
Buffer Mode
(PLL Bypass)
—2.5
ns
Output-Output Skew
tDSKEW
Rn divider = 11
——
100
ps
Programmable Initial
Phase Offset
POFFSET
–45
+45
ns
Phase Increment/Decrement
Accuracy
PSTEP
——
20
ps
Phase Increment/Decrement
Range
PRANGE
–45
+45
ns
Frequency range for phase
increment/decrement
fPRANGE
MHz
Phase Increment/Decrement
Update Rate
PUPDATE
Pin control
1500
kHz
Frequency Increment/
Decrement Step Size
fSTEP
R divider not used3
1
See
Note 2
ppm
Frequency Increment/
Decrement Range
fRANGE
R divider not used3
MHz
Frequency Increment/
Decrement Update Rate
fUPDATE
Pin control2,3
1500
kHz
Spread Spectrum PP
Frequency Deviation
SSDEV
Clock frequency of 100 MHz4
—–0.5
%
Spread Spectrum Modulation
Rate
SSDEV
Clock frequency of 100 MHz
30
33
kHz
Table 5. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Keep MultiSynth output frequency between 5 MHz to Fvco/8.
3. Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.
4. Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.
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