參數(shù)資料
型號: SI5326C-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/72頁
文件大?。?/td> 0K
描述: IC ANY-RATE MULTI/ATTEN 36-QFN
標準包裝: 490
系列: DSPLL®
類型: 時鐘放大器,振動衰減器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設備封裝: 36-QFN(6x6)
包裝: 管件
產(chǎn)品目錄頁面: 628 (CN2011-ZH PDF)
其它名稱: 336-1746
336-1746-5
336-1746-ND
Rev. 1.0 9/10
Copyright 2010 by Silicon Laboratories
Si5326
A NY F REQUENCY P RECISION C LO C K M ULT I PLI E R /J ITTER
A TTENUATO R
Features
Applications
Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The Si5326 can also use its crystal oscillator
as a clock source for frequency synthesis. The device provides virtually any
frequency translation combination across this operating range. The Si5326 input
clock frequency and clock multiplication ratio are programmable through an I2C or
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation
DSPLL technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications.
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps rms
(50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter
specifications
Dual clock inputs with manual or
automatically controlled hitless
switching (LVPECL, LVDS, CML,
CMOS)
Dual clock outputs with selectable
signal format
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjustment
I2C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
SONET/SDH OC-48/OC-192/STM-
16/STM-64 line cards
ITU G.709 and custom FEC line
cards
GbE/10GbE, 1/2/4/8/10G Fibre
Channel line cards
GbE/10GbE Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
xDSL
PDH clock synthesis
Test and measurement
Broadcast video
Ordering Information:
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RA
TE
0
CK
IN2
+
CK
IN2
NC
RA
TE
1
CK
IN
1+
CK
IN
1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CK
OU
T
1
NC
GN
D
VD
D
NC
CKO
U
T2
CKO
U
T2
+
CM
O
D
E
GND
Pad
A0
INC
9
18
19
28
XB
LO
L
DEC
CK
OU
T
1
+
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