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Si5316
6
Rev. 1.0
2-Level LVCMOS Input Pins
Input Voltage Low
VIL
VDD =1.71V
—
0.5
V
VDD =2.25V
—
0.7
V
VDD =2.97V
—
0.8
V
Input Voltage High
VIH
VDD =1.89V
1.4
—
V
VDD =2.25V
1.8
—
V
VDD =3.63V
2.5
—
V
Input Low Current
IIL
——
50
A
Input High Current
IIH
——
50
A
Weak Internal Input Pull-up
Resistor
RPUP
—75
—
k
Weak Internal Input
Pull-down Resistor
RPDN
—75
—
k
3-Level Input Pins
Input Voltage Low
VILL
——
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x VDD
—
0.55 x VDD
V
Input Voltage High
VIHH
0.85 x VDD
——
V
Input Low Current
–20
—
A
Input Mid Current
IIMM
–2
—
2
A
Input High Current
——
20
A
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most
designs, an external resistor voltage divider is recommended.