- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2016 > SI52143-A01AGM (Silicon Laboratories Inc)IC CLK GEN QUAD PCIE 24QFN PDF資料下載
參數(shù)資料
| 型號： | SI52143-A01AGM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN QUAD PCIE 24QFN |
| 標(biāo)準(zhǔn)包裝： | 92 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | 時鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 散裝 |
Si52143
8
Rev 1.2
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
2.2. OE Pin Definition
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable
the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins is required
to be driven at all time and even though it has an internally 100 k
resistor.
2.3. OE Assertion
The OE signals are active high input used for synchronous stopping and starting the output clocks respectively while
the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes
stopped respective output clocks to resume normal operation. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock
cycles.
2.4. OE Deassertion
When the OE pin is deasserted by making its logic low, the corresponding output clocks are stopped cleanly, and
the final output state is driven low.
2.5. SSON Pin Definition
SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is
enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread.
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 x CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI52144-A01AGM | IC CLK GENERATOR 100MHZ 24QFN |
| SI5315A-C-GM | IC CLK MULT 8KHZ-644.53MHZ 36QFN |
| SI5319A-C-GM | IC CLOCK MULT/ATTENUATOR 36QFN |
| SI5324A-C-GM | IC CLOCK MULT VARI FREQ 36VQFN |
| SL28504BZC-1 | IC CLOCK GEN EAGLELAKE 56TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si52143-A01AGMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIe G2 4 output from 25MHz input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI52144 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR |
| SI52144-A01AGM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIe G3 4 OUTPUT FROM 25MHZ INPUT RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si52144A01A-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si52144-A01AGMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIe family,4 output PCIe G3, 25MHz input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。