參數(shù)資料
型號: SI4711-B30-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 7/40頁
文件大?。?/td> 380K
描述: IC TX FM RADIO 76-108MHZ 20UQFN
標準包裝: 490
頻率: 76MHz ~ 108MHz
應(yīng)用: 通用
調(diào)制或協(xié)議: FM
電流 - 傳輸: 18.8mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.7 V ~ 5.5 V
封裝/外殼: 20-UFQFN 裸露焊盤
包裝: 托盤
Si4710/11-B30
Rev. 1.1
7
Table 5. 2-Wire Control Interface Characteristics
1,2,3
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= 20 to 85 癈)
Parameter
Symbol   Test Condition
Min
Typ
Max
Unit
SCLK Frequency
f
SCL
0

400
kHz
SCLK Low Time
t
LOW
1.3


SCLK High Time
t
HIGH
0.6


SCLK Input to SDIO?/SPAN> Setup
(START)
t
SU:STA
0.6


SCLK Input to SDIO?/SPAN> Hold (START)    t
HD:STA
0.6


SDIO Input to SCLK?/SPAN> Setup
t
SU:DAT
100


ns
SDIO Input to SCLK?/SPAN> Hold
4,5
t
HD:DAT
0

900
ns
SCLK input to SDIO?/SPAN> Setup (STOP)    t
SU:STO
0.6


STOP to START Time
t
BUF
1.3


SDIO Output Fall Time
t
f:OUT

250
ns
SDIO Input, SCLK Rise/Fall Time
t
f:IN
t
r:IN

300
ns
SCLK, SDIO Capacitive Loading
C
b


50
pF
Input Filter Pulse Suppression
t
SP


50
ns
Notes:
1.  When V
IO
= 0 V, SCLK and SDIO are low-impedance. 2-wire control interface is I
2
C compatible.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is 
high) does not occur within 300 ns before the rising edge of RST
.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST
, and stays high
until after the first start condition.
4. The Si4710/11 delays SDIO by a minimum of 300 ns from the V
IH
 threshold of SCLK to comply with the minimum t
5.
HD:DAT
 specification.
6. The maximum t
HD:DAT
 has only to be met when f
SCL
= 400 kHz. At frequencies below 400 KHz, t
HD:DAT
 may be
violated as long as all other timing parameters are met.
20   0.1
C
b
1 pF
------ ----- -
+
20   0.1
C
b
1 pF
------ ----- -
+
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