(VDD = 2.7 to 3.6 V, " />
參數(shù)資料
型號: SI4112-D-GT
廠商: Silicon Laboratories Inc
文件頁數(shù): 35/36頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER IF ONLY 24TSSOP
標準包裝: 62
類型: 頻率合成器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 管件
產品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: 336-1171
Si4133
8
Rev. 1.61
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
XIN Input Frequency
f
REF
2—
26
MHz
Reference Amplifier Sensitivity
VREF
0.5
VDD
+0.3 V
VPP
Phase Detector Update Frequency
f
f= fREF/R
0.010
1.0
MHz
RF1 VCO Center Frequency Range
fCEN
947
1720
MHz
RF1 VCO Tuning Range2
Extended frequency
operation
1850
2050
MHz
RF2 VCO Center Frequency Range
fCEN
789
1429
MHz
RF Tuning Range from fCEN
Note: LEXT ±10%
–5
5
%
IF VCO Center Frequency Range
fCEN
526
952
MHz
IFOUT Tuning Range
with IFDIV
62.5
1000
MHz
IFOUT Tuning Range from fCEN
Note: LEXT ±10%
–5
5
%
RF1 VCO Pushing
Open loop
500
kHz/V
RF2 VCO Pushing
400
kHz/V
IF VCO Pushing
300
kHz/V
RF1 VCO Pulling
VSWR = 2:1, all
phases, open loop
400
kHzPP
RF2 VCO Pulling
300
kHzPP
IF VCO Pulling
100
kHzPP
RF1 Phase Noise
1 MHz offset
–132
dBc/Hz
RF1 Integrated Phase Error
10 Hz to 100 kHz
0.9
degrees
rms
RF2 Phase Noise
1 MHz offset
–134
dBc/Hz
RF2 Integrated Phase Error
10 Hz to 100 kHz
0.7
degrees
rms
IF Phase Noise
100 kHz offset
–117
dBc/Hz
IF Integrated Phase Error
100 Hz to 100 kHz
0.4
degrees
rms
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO Tuning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN
or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN
, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN.
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