The Si3220-based Dual ProSLIC
參數(shù)資料
型號： SI3220PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 59/112頁
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標準包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3220
已供物品： 板，CD
Si3220/25 Si3200/02
50
Rev. 1.3
Not
Recommended
fo
r N
ew
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esi
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3.12. Ringing Generation
The Si3220-based Dual ProSLIC chipset provides a
balanced ringing waveform with or without dc offset.
The ringing frequency, cadence, waveshape, and dc
offset are register-programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand half the total ringing amplitude
seen across TIP-RING.
Figure 23. Balanced Ringing
An internal ringing scheme provides >40 Vrms into a 5
REN load at the terminal equipment using a user-
provided ringing battery supply. The specific ringing
supply voltage required depends on the desired ringing
voltage.
The
ringing
amplitude
at
the
terminal
equipment also depends on the loop impedance and
the load impedance in REN. The simplified circuit in
shows
the
relationship
between
loop
impedance and load impedance.
Figure 24. Simplified Loop Circuit During
Ringing
The following equation can be used to determine the
TIP-RING ringing amplitude required for a specific load
and loop condition:
where
and
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200/2 and may require
additional airflow or modified PCB layout to maintain
acceptable operating temperatures in the line feed
circuitry. The Dual ProSLIC chipset automatically
applies and removes the ringing signal during VOC-
crossing periods to reduce noise and crosstalk to
adjacent lines. Table 29 provides a list of registers
required for internal ringing generation
RING
TIP
V
RING
V
TIP
SLIC
V
OFF
GND
V
TIP
V
RING
V
BATH
V
PK
V
OV
V
CM
V
OFF
R
LOOP
V
RING
R
LOAD
V
TERM
+
–
R
OUT
V
TERM
V
RING
R
LOAD
R
LOAD
R
LOOP
R
OUT
++
---------------------------------------------------------------------
=
R
LOOP
0.09
per foot for 26AWG wire
=
R
OUT
320
=
R
LOAD
7000
#REN
--------------------
=
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相關代理商/技術參數(shù)
參數(shù)描述
SI3220-X-FQ 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL PROSLIC㈢ PROGRAMMABLE CMOS SLIC/CODEC
SI3220-X-GQ 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL PROSLIC㈢ PROGRAMMABLE CMOS SLIC/CODEC
SI3225 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL PROSLIC㈢ PROGRAMMABLE CMOS SLIC/CODEC
Si3225-BQ 功能描述:電信線路管理 IC DUAL CH SLIC CODEC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3225DC0-EVB 功能描述:子卡和OEM板 Si3225 Daughter Card RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
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