參數(shù)資料
型號： SI3220DC0-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 22/112頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3220
已供物品： 板，CD
Si3220/25 Si3200/02
Rev. 1.3
17
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 1. SPI Timing Diagram
Table 12. Switching Characteristics—SPI
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL =20 pF)
Parameter1
Symbol
Test Conditions
Min
Typ
Max
Unit
Cycle Time SCLK2
tc
62
—
ns
Rise Time, SCLK
tr
—
25
ns
Fall Time, SCLK
tf
—
25
ns
Delay Time, SCLK Fall to SDO Active
td1
—
20
ns
Delay Time, SCLK Fall to SDO
Transition
td2
—
20
ns
Delay Time, CS Rise to SDO Tri-state
td3
—
20
ns
Setup Time, CS to SCLK Fall
tsu1
25
—
ns
Hold Time, CS to SCLK Rise
th1
20
—
ns
Setup Time, SDI to SCLK Rise
tsu2
25
—
ns
Hold Time, SDI to SCLK Rise
th2
20
—
ns
Delay Time between Chip Selects
tcs
220
—
ns
SDI to SDITHRU Propagation Delay
td4
—
4
10
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VDDD –0.4 V, VIL =0.4 V
2. The minimum SCLK cycle time is based on a single Si3220 connected to the SPI bus. If multiple Si3220s are
connected to the same SPI bus, please contact a Silicon Laboratories representative for the recommended minimum
SCLK cycle time for your application.
SCLK
CS
SDI
t
h1
t
d3
SDO
t
d1
t
d2
t
su1
t
r
t
f
t
su2
t
h2
t
cs
t
c
SDITHRU
t
d4
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