參數(shù)資料
型號(hào): SI3018-F-FS
廠商: Silicon Laboratories Inc
文件頁數(shù): 75/94頁
文件大?。?/td> 0K
描述: IC ISOMODEM LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝: 48
系列: ISOmodem®
數(shù)據(jù)格式: V.92
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 管件
Si3056
Si3018/19/10
Rev. 1.05
77
Reset settings = 0000_0000
Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CVT[7:0]
Type
R/W
Bit
Name
Function
7:0
CVT[7:0]
Current/Voltage Threshold.
Determines the threshold at which an interrupt is generated from either the LCS or LVS regis-
ter. Generate this interrupt to occur when the line current or line voltage rises above or drops
below the value in the CVT[7:0] register.
Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 Line-Side Device Only)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CVI
CVS
CVM
CVP
Type
R/W
Bit
Name
Function
7:4
Reserved Read returns zero.
3CVI
Current/Voltage Interrupt.
0 = The current / voltage threshold has not been crossed.
1 = The current / voltage threshold is crossed. If the CVM and INTE bits are set, a hardware
interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared.
2CVS
Current/Voltage Select.
0 = The line current shown in the LCS2 register generates an interrupt.
1 = The line voltage shown in the LVS register generates an interrupt.
1CVM
Current/Voltage Interrupt Mask.
0 = The current / voltage threshold being triggered does not cause a hardware interrupt on the
AOUT/INT pin.
1 = The current / voltage threshold being triggered causes a hardware interrupt on the AOUT/
INT pin.
0CVP
Current/Voltage Interrupt Polarity.
0 = The current / voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register falling below the value in the CVT[7:0] register.
1 = The current / voltage threshold is triggered by the absolute value of the number in the
either the LCS2 or LVS register rising above the value in the CVT[7:0] Register.
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