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參數(shù)資料
| 型號(hào)： | SI3018-F-FS-R |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 29/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ISOMODEM LINE-SIDE DAA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | ISOmodem® |
| 數(shù)據(jù)格式： | V.92 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | Q5301285C |
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Si3056
Si3018/19/10
Rev. 1.05
35
5.22. Overload Detection
The Si3056 can be programmed to detect an overload
condition that exceeds the normal operating power
range of the DAA circuit. To use the overload detection
feature, the following steps should be followed:
1. Set the OH bit (Register 5, bit 0) to go off-hook, and
wait 25 ms to allow line transients to settle.
2. Enable overload detection by then setting the OPE
bit high (Register 17, bit 3).
If the DAA then senses an overload situation, it
automatically presents an 800
impedance to the line
to reduce the hookswitch current. At this time, the DAA
also sets the OPD bit (Register 19, bit 0) to indicate that
an overload condition exists. The line current detector
within the DAA has a threshold that is dependant upon
the ILIM bit (Register 26). When ILIM = 0, the overload
detection threshold equals 160 mA. When ILIM = 1, the
overload detection threshold equals 60 mA. The OPE
bit should always be cleared before going off-hook.
5.23. Gain Control
The Si3056 supports different gain and attenuation
settings depending on the line-side device being used.
For both devices, gains of 0, 3, 6, 9, and 12 dB can be
selected for the receive path with the ARX[2:0] bits. The
receive path can also be muted with the RXM bit.
Attenuations of 0, 3, 6, 9, and 12 dB can also be
selected for the transmit path with the ATX[2:0] bits. The
transmit path also can be muted with the TXM bit
(Register 15).
When using the Si3019 line-side device, the Si3056
provides even more flexible gain and attenuation
settings. The TXG2 and RXG2 bits (registers 38–39)
enable gain or attenuation in 1 dB increments up to
15 dB for the transmit and receive paths. The TGA2 and
RGA2 bits select either gain or attenuation for these
registers. The TXG3 and RXG3 bits (registers 40–41)
enable gain or attenuation in 0.1 dB increments up to
1.5 dB for the transmit and receive paths. The TGA3
and RGA3 bits select either gain or attenuation for these
registers. These additional gain/attenuation registers
are active only when the ARX[2:0] and ATX[2:0] bits are
set to all 0s.
Figure 24. Line-Side Device Signal Flow Diagram
Figure 25. Si3056 Signal Flow Diagram
To
Si3056
ADC
DAC
Link
Analog
Hybrid
ACT
TX
CO
Digital
Hybrid
IIRE
Digital
Filter
TXG2
To
Line-side
Device
Link
TXG3
TXA3
SDI
SDO
1 dB
Gain
Steps
0.1 dB
Gain/ATT
Steps
TXA2
1 dB
Attenuation
Steps
RXA2
1 dB
Attenuation
Steps
Digital
IIRE
Filter
RXG3
0.1 dB
Gain/ATT
Steps
RXA3
1 dB
Gain
Steps
RXG2
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