
Product Description
Sirenza Microdevices’ SHF-0189 is a high performance AlGaAs/GaAs
Heterostructure FET (HFET) housed in a low-cost surface-mount plastic
package. The HFET technology improves breakdown voltage while minimiz-
ing Schottky leakage current resulting in higher PAE and improved linearity.
Output power at 1dB compression for the SHF-0189 is +27 dBm when
biased for Class AB operation at 8V,100mA. The +40 dBm third order
intercept makes it ideal for high dynamic range, high intercept point require-
ments. It is well suited for use in both analog and digital wireless communi-
cation infrastructure and subscriber equipment including 3G, cellular, PCS,
fixed wireless, and pager systems.
The matte tin finish on Sirenza’s lead-free package utilizes a post anneal-
ing process to mitigate tin whisker formation and is RoHS compliant per EU
Directive 2002/95. This package is also manufactured with green molding
compounds that contain no antimony trioxide nor halogenated fire retar-
dants.
1
EDS-101240 Rev E
303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent
rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or
systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
SHF-0189
SHF-0189Z
Pb
0.05 - 6 GHz, 0.5 Watt
GaAs HFET
RoHS Compliant
&
Package
Green
Product Features
Now available in Lead Free, RoHS
Compliant, & Green Packaging
High Linearity Performance at 1.96 GHz
+27 dBm P1dB
+40 dBm Output IP3
+16.5 dB Gain
High Drain Efficiency
See App Note AN-031 for circuit details
Applications
Analog and Digital Wireless Systems
3G, Cellular, PCS
Fixed Wireless, Pager Systems
-5
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Typical Gain Performance (8V,100mA)
G
Frequency (GHz)
Gmax
Gain
S y m b o l
D e v ic e C h a r a c te r is tic s
T e s t C o n d itio n s , 2 5 C
V
(u n le s s o th e r w is e n o te d )
= 8 V , I
= 1 0 0 m A
T e s t
F r e q u e n c y
U n its
M in
T y p
M a x
G m a x
M a x im u m A v a ila b le G a in
Z
S
= Z
S
* , Z
L
= Z
L
*
0 .9 0 G H z
1 .9 6 G H z
d B
-
2 3 .3
2 0 .1
-
S
2 1
In s e rtio n G a in
[1 ]
Z
S
= Z
L
= 5 0 O h m s
0 .9 0 G H z
1 .9 6 G H z
d B
1 6 .6
1 8 .4
1 4 .7
2 0 .2
G a in
P o w e r G a in
[2 ]
A p p lic a tio n C irc u it
0 .9 0 G H z
1 .9 6 G H z
d B m
-
1 8 .6
1 6 .7
-
O IP 3
O u tp u t T h ird O rd e r In te rc e p t P o in t
[2 ]
A p p lic a tio n C irc u it
0 .9 0 G H z
1 .9 6 G H z
d B m
-
4 0
4 0
-
P 1 d B
O u tp u t 1 d B C o m p re s s io n P o in t
[2 ]
A p p lic a tio n C irc u it
0 .9 0 G H z
1 .9 6 G H z
d B m
-
2 7 .2
2 7 .5
-
N F
N o is e F ig u re
A p p lic a tio n C irc u it
1 .9 6 G H z
d B
-
3 .2
-
I
D S S
S a tu ra te d D ra in C u rre n t
V
D S
= V
D S P
, V
G S
= 0 V
m A
2 0 4
2 9 4
3 8 4
g
m
T ra n c o n d u c ta n c e
V
D S
= V
D S P
, V
G S
= -0 .2 5 V
m S
1 4 4
1 9 8
2 5 2
V
P
P in c h -O ff V o lta g e
[1 ]
V
D S
= 2 .0 V , I
D S
= 0 .6 m A
V
-3 .0
-1 .9
-1 .0
B V
G S
G a te -S o u rc e B re a k d o w n V o lta g e
[1 ]
I
G S
= 1 .2 m A , d ra in o p e n
V
-
-1 7
-1 5
B V
G D
G a te -D ra in B re a k d o w n V o lta g e
[1 ]
I
G D
= 1 .2 m A , V
G S
= -5 .0 V
V
-
-2 2
-1 7
R th
T h e rm a l R e s is ta n c e
ju n c tio n -to -le a d
o
C /W
-
8 0
-
V
D S
O p e ra tin g V o lta g e
[3 ]
d ra in -s o u rc e
V
-
-
8 .0
I
D Q
O p e ra tin g C u rre n t
[3 ]
d ra in -s o u rc e , q u ie s c e n t
m A
-
-
1 6 0
P
D IS S
P o w e r D is s ip a tio n
[3 ]
W
-
-
0 .8
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board.
The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR.
[3] Maximum recommended power dissipation is specified to maintain T
J
<150C at T
L
=85C. V
DS
* I
DQ
<0.8W is recommended for continuous reliable operation.