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參數(shù)資料
| 型號： | SEL4824E-FREQT |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 200 MHz - 670 MHz, PECL OUTPUT |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 332K |
| 代理商： | SEL4824E-FREQT |
Crystal Clock Oscillator
Technical Data
SEL481 / SEL482 Series
3.3V, PECL, FR4
DS-235 REV A 08/02/04
www.pericom.com
Output Enable/Disable for SEL482x:
Output Enable:
Output Disable:
Frequency Range:
200 MHz to 670 MHz
Description
ACTUAL SIZE
Applications & Features
SONET/SDH/DWDM linecards
XGigE NICs
Optical SOHO FTTC/FTTP OC-12
& STM-4 first/last mile networking
3.3V PECL (LVPECL) capability
Frequency range from 200 to
670MHz
Disable output feature available
Economical and rugged FR4 package
Guaranteed long-term aging avail-
able, consult SaRonix for details
Designed for standard reflow and
washing techniques
Available on tape & reel; 16mm tape,
500pcs per reel
See SEL393x Series for frequencies
≤ 200MHz
See SEL381x Series for comparable
performance in a smaller ceramic
5x7mm package
See SDS3811 Series for new LVDS
capability in a smaller ceramic
5x7mm package
±20, ±25, ±50 or ±100 ppm over all conditions: calibration tolerance,
operating temperature, rated input (supply) voltage, load, *aging, shock
and vibration.
30 days (±7ppm in 10 years typical)
Frequency Stability:
*Aging:
Temperature Range:
Operating:
Storage:
Supply Voltage (V
CC
):
+3.3V PECL
-55 to +125°C
Supply Current:
85mA typ, 110mA max
0 to +70°C or -40 to +85°C
Output Drive:
Symmetry:
Rise & Fall Times:
Logic 0:
Logic 1:
Load:
Accumulated Jitter:
Phase Jitter:
Total Jitter:
Output Enable Voltage:
Disable Voltage:
45/55% max @ V
BB
or Complementary Outputs Crossing
550ps typ, 850ps max, 20% to 80% of waveform
≤ V
CC
-1.620V (-40 to 85°C )
≥ V
CC
-1.025V (0 to +70°C), V
CC
-1.085V (-40 to 85°C)
50Ω to V
CC
-2V
10ps RMS (1-sigma) max, accumulated in 20,000 adjacent periods
3ps RMS (1-sigma) max, in 12kHz to 40MHz Freq. Band
50ps peak-to-peak max in 100,000 random periods
≤ Level 0 or open
≥ Level 1 (Q & Q outputs disabled to High Impedance)
≥ Level 1 or open
≤ Level 0 (Q & Q outputs disabled to High Impdeance)
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Resistance to Soldering Heat:
Solvent Resistance:
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-883, Method 2004, Condition D
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 210, Condition I or J
MIL-STD-202, Method 215
Environmental:
Thermal Shock:
Moisture Resistance:
MIL-STD-883, Method 1011, Condition A
MIL-STD-833, Method 1004
Solder Reflow Guide
Output Enable/Disable for SEL481x (n/a for SEL4810):
A crystal controlled, high frequency,
highly stable oscillator, compatible with
LVPECL logic. The output can be disabled
to facilitate testing or combining with mul-
tiple clocks. The oscillator is packaged
in leadless SMD FR4 SO20 available in
four (4) or six (6) pad configurations (see
part number builder) and achieves excep-
tional frequency stability. This oscillator
is ideal for today's automated assembly
environments.
Output Waveform
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