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參數(shù)資料
| 型號： | SDM862B |
| 英文描述： | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| 中文描述： | 16單端/ 8差分輸入12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 10/27頁 |
| 文件大小： | 256K |
| 代理商： | SDM862B |
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SDM862/863/872/873
10
acquisition time and droop rate, as the hold capacitor is
increased in value it takes longer to charge, and hence there
is a corresponding increase in acquisition time and reduction
in droop rate. The droop rate is determined by the amount of
leakage present in the SDM, board leakage and the dielectric
absorption of the hold capacitance. The hold capacitor is
also a compensation element for the S/H and should not be
reduced below 2nf for good stability. The offset error in
sample mode is not affected by the hold capacitor. However,
during the transition to hold mode there is approximately
5pC of charge injected into the hold capacitor, causing an
offset error that has been nulled for use with a 5nf hold
capacitor. Any other value for the hold capacitor will cause
a minor but fixed hold mode offset to be introduced, and is
proportional to the change in value from 5nf. Therefore, the
SDM should be offset nulled with the S/H in hold mode.
ANALOG-TO-DIGITAL CONVERTER
This circuit element converts the analog voltage presented
by the sample/hold amplifier to a digital number in binary
format under control of the digital signals detailed in Figure
9. The converter can convert unipolar and bipolar signals in
the range 10V and 20V. It can be calibrated to remove gain
and offset errors from the entire system. The converter
contains its own clock, voltage reference, and microproces-
sor interface with 3-state outputs. The converter will nor-
mally be used to digitize signals to 12-bit resolution, but it
can be short-cycled to provide 8-bit resolution at higher
speed. The digital output is compatible with 8- or 16-bit data
buses, the data format being selected by control signals as
detailed in Figure 9.
SAMPLE/HOLD AMPLIFIER
The Sample/Hold amplifier (S/H) is used to track the incom-
ing signal and “hold” the required instantaneous value so
that it does not change while the ADC is carrying out its
conversion. Timing for the S/H may be derived from the
STATUS output of the ADC, with care being taken to
comply with the SDM timing considerations.
Capacitors with high insulation resistance and low dielectric
absorption such as Teflon, polystyrene or polypropylene
should be used as storage elements. (Polystyrene should not
be used above +80
°
C.) Teflon is recommended for high
temperature operation. Care should be taken in the printed
circuit layout to minimize stray capacitance and leakage
currents from the capacitor to minimize charge offset and
droop errors. The use of a guard ring driven by the S/H
output around the pin connecting to the hold capacitor is
recommended. (Refer to the application board layout for an
example of this.)
The value of the external hold capacitor determines the
droop rate, charge offset and acquisition time of the S/H,
Figure 8. Droop rate for the SDM is specified with a hold
capacitor value of 4700pf. There is a trade-off between
FIGURE 7. Setting Programmable Gains.
Some applications may require programmable gains. This
may be realized with Figure 7.
1
2
3
15
66
6
7
8
67
SDM8X3
MUX
INA
Gain Sel
TTL/CMOS
1-10-100
PGA
102
FIGURE 8. Acquisition Time vs Hold Capacitance for a 10V
Step Settling to
±
10mV of Final Value.
DATA
MODE
BYTE
SELECT
CE
CS
R/C
OPERATION
0
X
1
1
1
1
1
1
1
X
1
0
0
0
0
0
0
0
X
X
0
0
0
0
1
1
1
X
X
X
X
X
X
X
X
1
0
0
X
X
0
1
0
1
0
1
X
0
1
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus 4
trailing zeros
FIGURE 9. Control Input Truth Table.
LINEARITY ERROR
Linearity error is defined as the deviation of actual code
transition values from the ideal transition values. Ideal
transition values lie on a line drawn through zero (or minus
full scale for bipolar operation) and plus full scale. The zero
value is located at an analog input value 1/2LSB before the
first code transition (000
H
to 001
H
). The full-scale value is
located at an analog value 3/2LSB beyond the last code
transition (FFE
H
to FFF
H
) (see Figure). Thus, with the SDM
connected for bipolar operation and with a full-scale range
(or span) of 20V (
±
10V), the zero value of –10V is 2.44mV
6
10
9
8
7
6
5
4
3
8
4
10
12
14
16
A
Hold Capacitance (nF)
ACQUISITION TIME vs HOLD CAPACITANCE
For a 10V Step to ±10mV of Final Value
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SDM862J | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862K | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862R | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862S | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM863 | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDM862J | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862K | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862R | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM862S | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM863 | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
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