參數(shù)資料
型號: SDA9489X
廠商: Electronic Theatre Controls, Inc.
英文描述: PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs
中文描述: 畫中畫四先進(jìn)SOPHISTICUS高端畫中畫,圖像芯片
文件頁數(shù): 37/102頁
文件大?。?/td> 2306K
代理商: SDA9489X
Micronas
4-37
SDA 9489X
SDA 9589X
System Description
Preliminary Data Sheet
the clamping and blanking pulse because of the modified clock frequency, but the pulse
length is kept nearly constant.
Figure 4-20
PIP horizontal blanking timing
Table 4-21
PIP horizontal blanking timing
4.10.1
The pedestal level adjustment controlled by I
2
C signals
BLKLR
,
BLKLG
,
BLKLB
enables the correction of small offset errors, possibly appearing at the successive
blanking stage of RGB processor. This adjustment has an effect on the setup level
during the active line interval of each channel like the brightness adjustment but has an
Pedestal Level Adjustment
READD
CLPDEL
CLPLEN
a (
s)
Blanking
Start
b (
s)
Blanking
Duration
c (
s)
Clamping
Start
d (
s)
Clamping
Duration
D2
D1
D0
D1
D0
0
0
0
0
0
0
-1.5
10.5
3
5
0
1
1
1
0
0
-11
10.5
-6.4
5
0
0
0
0
0
1
-1.5
7.9
2.2
3.8
0
1
1
1
0
1
-11.0
7.9
-7.3
3.8
1
0
0
0
0
0
-0.8
5.3
1.5
2.5
1
1
1
1
0
0
-5.5
5.3
-3.2
2.5
1
0
0
0
0
1
-0.8
4
1.1
1.9
1
1
1
1
0
1
-5.5
4
-3.6
1.9
BLANKP
HSP
CLAMPP
a
Parent
Video
allowed
HSP range
256 T
b
d
c
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