參數(shù)資料
型號(hào): SDA5275-2P
廠商: SIEMENS A G
元件分類(lèi): 圖文
英文描述: ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs
中文描述: TELETEXT DECODER, PQCC68
文件頁(yè)數(shù): 19/30頁(yè)
文件大?。?/td> 142K
代理商: SDA5275-2P
SDA 5273 / 75
SDA 5273-2 / 75-2
Semiconductor Group
19
1997-09-01
Characteristics
(cont’d)
T
A
= 0 to 70
°
C
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
DRAM-Interface (see diagram 5)
The external DRAM is operated in page mode.
The timing of the DRAM-interface signals are specified below.
Cycle time
t
WC
t
RAH
t
CAH
t
ASR
420
500
550
ns
Address hold time from RAS
25
ns
Address hold time from CAS
60
ns
Address set-up time from
RAS
5
ns
Address set-up time from
CAS
t
ASC
5
ns
L-time RAS
t
RASP
t
CASL
t
RP
t
CP
280
ns
L-time CAS
70
ns
H-time RAS
140
ns
H-time CAS
70
ns
Refresh period
20
ms
Write Cycle
L-time WE
t
WEL
t
DS
t
RCS
t
DH
t
OHZ
210
ns
Data set-up time to CAS
100
ns
WE set-up time to CAS
0
ns
Data hold time from CAS
55
ns
Data hold time from WE
10
ns
Read Cycle
H-time WE (output enable)
t
OEL
t
CAC
t
OFF
210
ns
Access time from CAS
60
ns
Data hold time of DRAM
40
ns
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