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參數(shù)資料
| 型號： | SDA4331X |
| 廠商： | SIEMENS A G |
| 元件分類： | XO, clock |
| 英文描述： | PLL with I2C Bus for AM/FM Receivers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 155 MHz, PDSO24 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 446K |
| 代理商： | SDA4331X |
SDA 4331X
Semiconductor Group
5
04.96
2
The SDA 4331X is a radio PLL controlled via
I
2
C Bus for frequency synthesis in the AM
and FM range.
Functional Description
3
The reference frequency for the PLL is derived from the quartz oscillator OSC
1)
. The
R-prescaler can be adapted to quartz frequencies of 4, 8 or 10.25 MHz, respectively,
yielding an internal 50 kHz reference. Programming the R-counter sets the phase
detector reference frequency to 1, 5 or 10 kHz in the AM mode or to 12.5, 25 or 50 kHz
in the FM mode. The VCO frequency is set by programming the A/N-counter which
operates as dual-modulus counter for FM and AM using a divide by 4/5 swallow counter.
The phase detector drives two different charge pumps for AM and FM mode. Additional
source followers are connected to the charge pump. There are four programmable
current levels for each charge pump. The supply voltage for the charge pump and the
source followers is supplied via the
V
DD2
pin and can reach 10 V maximum. AM/FM is an
open drain output as well as the additional outputs SA1 … SA4 which are controlled by
I
2
C Bus.
The
I
2
C Bus interface provides slave receiver functions. There are two addresses
selected by the A0 pin. The
I
2
C-protocol (see
diagram 1
) contains one string for
programming all counters and functions. The transfer may be stopped optionally after
each word if the remaining functions are not to be altered. After power ON all control
signals are undefined, so that the complete write sequence must be executed.
Circuit Description
1)
The power dissipation of the quartz is given by:
P
v
= 2
×
R
1
(
Π ×
f
Q
×
(
C
O
+
C
L
)
×
V
DD
)
2
R
1
… Series resistance of the quartz
f
Q
… Quartz frequency
C
O
… Parallel capacitance of the quartz
C
L
… Load capacitance, including input capacitance of the IC
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