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參數(shù)資料
| 型號(hào)： | SDA2546-5 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 153K |
| 代理商： | SDA2546-5 |
Circuit Description
I
2
C Bus Interface
The
I
2
C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a data line SDA and a clock line SCL. The data line requires an external pull-up resistor
to
V
CC
(open drain output stages).
The possible operational states of the
I
2
C Bus are shown in
figure 1
. In the quiescent state, both
lines SDA and SCL are high, i.e. the output states are disabled. As long as SCL remains "1",
information changes on the data bus indicate the start or the end of a data transfer between two
components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1"
a stop condition. During a data transfer the information on the data bus will only change when the
clock line SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an
I
2
C Bus system, the device can operate as a receiver, and as a transmitter
(slave receiver/listener, or slave transmitter/talker). Between the falling edge of the eighth
transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a
reception confirmation, if the chip select conditions have been met. During the output of data, the
data output of the memory becomes high, during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the
I
2
C Bus is summarized in
figure 2
.
Nonvolatile Memory 4-Kbit E
2
PROM
with
I
2
C Bus Interface
Preliminary Data
MOS IC
SDA 2546-5
P-DIP-8-1
Features
G
Word-organized reprogrammable nonvolatile memory
in n-channel floating-gate technology (E
2
PROM)
G
512
×
8-bit organization
G
Supply voltage 5 V
G
Serial 2-line bus for data input and output (
I
2
C Bus)
G
Reprogramming mode, 10 ms erase/write cycle
G
Reprogramming by means of on-chip control (without
external control)
G
The end of the programming cycle can be checked
G
Data retention in excess of 10 years
G
More than 10
4
reprogramming cycles per address
Type
Ordering Code
Package
SDA 2546-5
Q67100-H5096
P-DIP-8-1
Semiconductor Group
29
07.94
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