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參數(shù)資料
| 型號： | sda 9290-6 |
| 廠商： | SIEMENS AG |
| 英文描述： | Picture Processor(圖象處理器) |
| 中文描述： | 圖像處理器（圖象處理器） |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 224K |
| 代理商： | SDA 9290-6 |
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SDA 9290-6
Semiconductor Group
13
1997-07-22
Pin Definitions and Functions
Pin No. Symbol
Function
Description
1
V
DD
Positive supply
voltage (+ 5 V)
Positive supply voltage (+ 5 V)
2-9
UVQ7 …
UVQ0
Data outputs
Push-pull outputs for directly driving the TV-SAM
chrominance inputs:
8 bits for 4:2:2 format;
4 bits for 4:1:1 format;
[UVQ0 … UVQ3 only valid for 4:2:2 format]
10
GND
Ground
Ground (0 V)
11-18
UVB0 …
UVB7
Back-channel
data outputs
Back-channel inputs for chrominance data from TV-SAM
19-26
YB0 …
YB7
Back- channel
data inputs
Back-channel inputs for luminance data from TV-SAM
27-34
UVI0 …
UVI7
Data inputs
Data inputs for chrominance data accept the dig. YUV
signal
35-42
YI0 …
YI7
Data inputs
Data inputs for luminance data accept the dig. YUV
signal
43
DREQ
Data request
signal for multi-
picture mode
Data-request input; initiates data transfer in multi-picture
mode and switches mode together with signal VS1
44
GND
Ground
Ground (0 V)
45
BLN
Blanking signal
(15.625 kHz)
Input for line-synchronous blanking signal that
determines line blanking interval (active low) and
synchronizes clock and sequence control
46
LLIN
First system clock
(13.5 MHz)
Input for line-locked system clock, 13.5 MHz, from which
internal timing is derived. Positive edge indicates validity
of input data
Must be connected to
V
DD
(high-level)
Input for line-locked 13.5-MHz clock that ensured picture
stability in multi-picture mode and is used as output clock
in every mode
47
LLSEL
none
48
LL3X
Second system
clock (13.5 MHz)
49
SCL
I
2
C Bus shift clock
input
I
2
C-Bus shift-clock input
50
SDA
I
2
C Bus data
input/output
I
2
C-Bus data input/output
51
VS1
Vertical sync input
(50 Hz)
Vertical sync input; determines vertical position of TV
picture for 50-Hz or 60-Hz field frequency
52
V
DD
Positive supply
voltage (+ 5 V)
Positive supply voltage (+ 5 V)
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