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| 型號： | SD-14531F2-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| 封裝： | CERAMIC, DFP-40 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 272K |
| 代理商： | SD-14531F2-202 |
ProASIC3/E Flash Family FPGAs
2- 2
v2.1
Device Overview
The ProASIC3 device family consists of five distinct
programmable architectural features (Figure 2-2 and
Core Architecture
VersaTile
The proprietary ProASIC3 family architecture provides
granularity comparable to gate arrays. The ProASIC3
device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-4 on page 2-4, there are four
inputs in a logic VersaTile cell, and each VersaTile can be
configured
using
the
appropriate
Flash
switch
connections:
Any 3-input logic function
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set (on a fourth
input)
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions can be connected with
any of the four levels of routing hierarchy.
When the VersaTile is used as an enable D-flip-flop,
SET/CLR is supported by a fourth input. The SET/CLR
signal can only be routed to this fourth input over the
VersaNet (global) network. However, if in the user’s
design the SET/CLR signal is not routed over the VersaNet
network, a compile warning message will be given and
the intended logic function will be implemented by two
VersaTiles instead of one.
The output of the VersaTile is F2 (Figure 2-4 on page 2-4)
when the connection is to the ultra-fast local lines, or YL
when the connection is to the efficient long-line or very-
long-line resources.
Note: *Not supported by A3P030.
Figure 2-2 ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
VersaTile
CCC
I/Os
ISP AES
Decryption*
User Nonvolatile
FlashROM
Charge Pumps
Bank 0
Bank
1
Bank
1
Bank
0
Bank
0
Bank 1
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