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參數(shù)資料
| 型號： | SD-14531D2-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PDIP36 |
| 封裝： | KOVER, DDIP-36 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 272K |
| 代理商： | SD-14531D2-202 |
ProASIC3/E Flash Family FPGAs
v2.1
1-1
Introduction and Overview
General Description
ProASIC3, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASICPLUS family. Nonvolatile Flash
technology gives ProASIC3 devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up (LAPU). ProASIC3 is reprogrammable
and offers time-to-market benefits at an ASIC-level unit
cost. These features enable designers to create high-
density systems using existing ASIC or FPGA design flows
and tools.
ProASIC3
devices
offer
1
kbit
of
on-chip,
reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated
phase-locked loop (PLL). The A3P030 device has no PLL or
RAM support. ProASIC3 devices have up to 1 million
system gates, supported with up to 144 kbits of true
dual-port SRAM and up to 288 user I/Os.
ProASIC3 devices support the ARM7 soft IP core in
devices with at least 250 k system gates. The ARM-
enabled devices have Actel ordering numbers that begin
with M7A3P and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs,
Flash-based
ProASIC3
devices
allow
all
functionality to be live at power-up; no external boot
PROM
is
required.
On-board
security
mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers
can
perform
secure
remote
in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3 family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3 family a cost-effective
ASIC replacement solution, especially for applications in
the consumer, networking/ communications, computing,
and avionics markets.
Security
The nonvolatile, Flash-based ProASIC3 devices do not
require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. ProASIC3 devices
incorporate
FlashLock,
which
provides
a
unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile Flash programming can offer.
ProASIC3 devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted
prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces
the 1977 DES standard. ProASIC3 devices have a built-in
AES decryption engine and a Flash-based AES key that
make them the most comprehensive programmable logic
device security solution available today. ProASIC3 devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3 device cannot be
read back, although secure design verification is possible.
ARM-enabled ProASIC3 devices do not support user-
controlled AES security mechanisms. Since the ARM core
must be protected at all times, AES encryption is always
on for the core logic, so bitstreams are always encrypted.
There is no user access to encryption for the FlashROM
programming data.
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3 family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The ProASIC3 family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible.
An
ProASIC3
device
provides
the
most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information
in
on-chip
Flash
cells.
Once
programmed,
the
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SD-14531D3-205 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PDIP36 |
| SD-14531F1-204 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F2-202 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F3-204 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F1-802 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
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