參數(shù)資料
型號(hào)： SCS156
廠商： Microchip Technology Inc.
英文描述： Reloadable Token Card Chip(KeeLoq 表示卡芯片)
中文描述： 增值令牌卡芯片（而Keeloq表示卡芯片）
文件頁數(shù)： 86/170頁
文件大小： 4191K
代理商： SCS156
PIC16F62X
DS40300C-page 84
Preliminary
2003 Microchip Technology Inc.
FIGURE 12-14:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
12.5
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP
instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit.
b)
The second word will remain in TXREG register.
c)
Flag bit TXIF will not be set.
d)
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e)
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the TXREG
register.
CREN BIT
RB1/RX/DT PIN
RB2/TX/CK PIN
WRITE TO
BIT SREN
SREN BIT
RCIF BIT
(INTERRUPT)
READ
RXREG
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q2
Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
'0'
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
'0'
Q1Q2Q3Q4
Note 1:
Timing diagram demonstrates Sync Master mode with bit SREN = ‘1’ and bit BRG = ‘0’.
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