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參數資料
| 型號： | SCS152 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | HM Series Hermetically Sealed Basic Switch, Single Pole Double Throw Circuitry, 0.5 A at 28 Vdc, Integral Lever Actuator, Solder Termination |
| 中文描述： | 而Keeloq令牌卡芯片 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 182K |
| 代理商： | SCS152 |
SCS152
1997 Microchip Technology Inc.
Preliminary
DS40150B-page 13
8.0
TABLE 8-1:
DEVICE CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Min.
Max.
Units
Supply voltage, with respect to GND
Input voltage, with respect to GND
Storage temperature
ESD protection on all pins (HBM)
V
DD
V
I
T
S
V
ESD
-0.3
-0.3
-55
—
6.0
6.0
+85
4000
V
V
°
C
V
TABLE 8-2:
V
DD
: 5.0 V
±
10%
T
A
:
-40
°
C to +85
°
C
DC CHARACTERISTICS
Description
Symbol
Min.
Typ.
Max.
Units
Condition
Current when reading
Current when programming
Input low voltage
Input high voltage
Output low voltage
I
DDR
I
DDP
V
IL
V
IH
V
OL
—
—
—
3.0
—
300
1.2
—
—
—
600
1.6
0.8
—
0.4
μ
A
mA
V
V
V
SDIO = V
DD
SDIO = V
DD
Sinking current, Io = 1 mA
TABLE 8-3:
V
DD
: 5 V
±
10%
T
A
:
-40
°
C to +85
°
C
R
PU
= 10K
AC CHARACTERISTICS
Description
Symbol
Min.
Typ.
Max.
Units
Time from V
DD
high until device accepts com-
mands
Overlap of SCI with SCK during RESET
Overlap period of SCI and SCK during RESET
SCK high
SCK low
SCK/SCI falling to SCI changing for BITPROG,
ERASE, etc.
SCI high pulse during BITPROT, ERASE, etc.
SDIO changing from falling edge of SCI/SCK
during RESET
SDIO changing from falling edge of SCK during
RDBIT
SDIO tri-state after rising edge of SCK
Time to program EEPROM during BITPROG,
ERASE, DECR-ERASE, etc.
Time to compute signature from falling edge of
SCK where last challenge bit is entered
T
POR
—
—
3.5
ms
T
OX
T
R
T
H
T
L
2.0
35.0
10.0
10.0
—
—
—
—
—
—
—
—
μ
s
μ
s
μ
s
μ
s
T
C
5.0
—
—
μ
s
T
S
2.0
—
—
μ
s
T
D
1
—
1.8
—
μ
s
T
D
2
—
1.8
4.7
μ
s
T
D
3
4.5
—
μ
s
T
PROG
1.4
—
3.4
ms
T
SIGN
—
—
2.5
ms
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