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參數(shù)資料
| 型號(hào)： | SCAN182245AMTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Non-Inverting Transceiver with 25ohm Series Resistor Outputs |
| 中文描述： | SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 145K |
| 代理商： | SCAN182245AMTD |
www.fairchildsemi.com
8
S
SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane
applications. It provides 2nd Level Isolation
1
which indi-
cates that while external circuitry to control the output
enable pin is unnecessary, there may be a need to imple-
ment differential length backplane connector pins for V
CC
and GND. As well, pre-bias circuitry for backplane pins
may be necessary to avoid capacitive loading effects dur-
ing live insertion.
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure 1. It essentially con-
trols the G
n
pin until V
CC
reaches a known level.
During
power-up
, when V
CC
ramps through the 0.0V to
0.7V range, all internal device circuitry is inactive, leaving
output and I/O pins of the device in high impedance. From
approximately 0.8V to 1.8V V
CC
, the Power-On-Reset cir-
cuitry, (POR), in Figure 1 becomes active and maintains
device high impedance mode. The POR does this by pro-
viding a low from its output that resets the flip-flop The out-
put, Q, of the flip-flop then goes high and disables the NOR
gate from an incidental low input on the G
n
pin. After 1.8V
V
CC
, the POR circuitry becomes inactive and ceases to
control the flip-flop. To bring the device out of high imped-
ance, the G
n
input must receive an inactive-to-active transi-
tion, a high-to-low transition on G
n
in this case to change
the state of the flip-flop. With a low on the Q output of the
flip-flop, the NOR gate is free to allow propagation of a G
n
signal.
During
power-down
, the Power-On-Reset circuitry will
become active and reset the flip-flop at approximately 1.8V
V
CC
. Again, the Q output of the flip-flop returns to a high
and disables the NOR gate from inputs from the G
n
pin.
The device will then remain in high impedance for the
remaining ramp down from 1.8V to 0.0V V
CC
.
Some suggestions to help the designer with live insertion
issues:
The G
n
pin can float during power-up until the Power-
On-Reset circuitry becomes inactive.
The G
n
pin can float on power-down only after the
Power-On-Reset has become active.
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of Figure 2.
FIGURE 1.
1
Section 7,
“
Design Consideration for Fault Tolerant Backplanes
”
, Application Note AN-881.
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
FIGURE 2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN182245AMTDX | 功能描述:總線收發(fā)器 FINISHED GOOD RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SCAN182245ASSC | 功能描述:總線收發(fā)器 Non-Inverting Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SCAN182245ASSCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Non-Inverting Transceiver with 25OHM Series Resistor Outputs |
| SCAN182245ASSCX | 功能描述:總線收發(fā)器 Non-Inverting Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SCAN182245ASSMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Non-Inverting Transceiver with 25OHM Series Resistor Outputs |
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