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參數(shù)資料
| 型號： | SC8863-300CSK |
| 廠商： | Semtech Corporation |
| 英文描述： | 150mA ULTRA LOW DROPOUT, LOW NOISE REGULATOR |
| 中文描述： | 150mA的超低壓降，低噪聲穩(wěn)壓器 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 92K |
| 代理商： | SC8863-300CSK |
150mA ULTRA LOW DROPOUT,
LOW NOISE REGULATOR
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
SC8863
March 1, 2000
8
bility may be improved by increasing C2 to 2.2μF and
reducing R2 to 10k
. See “Component Selection -
General” for input capacitor requirements.
Thermal Considerations
The worst-case power dissipation for this part is given
by:
(
MIN
MAX
)
MAX
(
D
VO
VIN
P
=
For all practical purposes, it can be reduced to:
(
MAX
)
MAX
(
D
VO
VIN
P
=
Looking at a typical application:
VIN
(MAX)
= 4.2V
VO = 3V - 3.5% worst-case
I
O
= 150mA
T
A
= 85°C
(
2
4
P
)
MAX
(
D
=
Using this figure, we can calculate the maximum ther-
mal impedance allowable to maintain T
J
≤
150°C:
(
P
)
MAX
(
D
With the standard SOT-23-5 Land Pattern shown at
the end of this datasheet, and minimum trace widths,
the thermal impedance junction to ambient for SC8863
is 256°C/W. Thus with no additional heatsinking,
T
J(MAX)
= 135°C.
The junction temperature can be further reduced by
the use of larger trace widths, and connecting pcb cop-
per area to the GND pin (pin 2), which connectes di-
rectly to the device substrate. Adding approximately
one square inch of pcb copper to pin 2 will reduce
θ
TH(J-A)
to approximately 130°C/W and T
J(MAX)
to ap-
proximately 110°C, for example. Lower junction tem-
peratures improve overall output voltage accuracy. A
sample pcb layout for the Internally Preset Output Volt-
age circuit on page 2 is shown in Figure 2 below.
Layout Considerations
While layout for linear devices is generally not as criti-
cal as for a switching application, careful attention to
detail will ensure reliable operation. See Figure 2 below
for a sample layout.
1) Attaching the part to a larger copper footprint will
enable better heat transfer from the device, especially
on PCBs where there are internal ground and power
planes.
2) Place the input and output capacitors (and the ca-
pacitor from OUT to SET for adjustable applications)
close to the device for optimal transient response and
device behaviour.
3) Connect all ground connections directly to the
ground plane. If there is no ground plane, connect to a
common local ground point before connecting to board
ground.
)
(
)
W
/
C
332
196
.
85
150
T
T
)
MAX
(
A
)
MAX
(
)
MAX
)(
A
J
(
°
=
=
=
θ
(
)
(
)
)
)
MAX
(
Q
)
MAX
(
)
MAX
(
O
I
VIN
I
+
(
)
(
)
)
)
MAX
(
O
MIN
I
)
mW
196
150
.
0
895
.
2
=
Top Copper
Top Silk Screen
Figure 2: Suggested pcb layout based upon internally preset output voltage application on page 2.
NOTES:
(1) All vias go to the ground plane.
(2) Copper area on pin 2 is recommended, but not required. Connect to the ground plane with a via or vias.
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