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參數(shù)資料
| 型號(hào)： | SC8164 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux |
| 中文描述： | 2.488 Gb /秒的2.7Gbit/sec 1:16的SONET / SDH解復(fù)用 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 153K |
| 代理商： | SC8164 |
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VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
G52239-0, Rev. 3.3
VITESSE SEMICONDUCTOR CORPORATION
Page 1
5/17/00
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Features
General Description
The VSC8164 is a 1:16 demultiplexer for use in SONET/SDH systems operating at a standard 2.488Gb/s
data rate or forward error correction (FEC) data rate up to 2.7Gb/s. The device operates using a single 3.3V
power supply, and is packaged in a thermally enhanced plastic package. The thermal performance of the
128PQFP allows the use of the VSC8164 without a heat sink under most thermal conditions.
VSC8164 Block DIagram
Functional Description
Low Speed Interface
The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D[15:0] with
accompanying differential LVPECL divide by 16 clock CLK16O± and divide by 32 clock CLK32O±. The low
speed LVPECL output drivers are designed to drive a 50
transmission line. The transmission line can be DC
terminated with a split end termination scheme (see Figure 1), or DC terminated by 50
to V
CC-2V on each line
(see Figure 2). At any time, the equivalent split-end termination technique can be substituted for the traditional
50
to V
CC-2V on each line. AC coupling can be achieved by a number of methods. Figure 3 illustrates an AC
coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the
downstream device were to have internal termination, the line to line 100
resistor may not be necessary. The
divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.
2.488Gb/s 1:16 Demultiplexer
Targeted for SONET OC-48 / SDH STM-16
Applications
Supports FEC rates up to 2.7Gb/s
Differential LVPECL Low Speed Interface
Single +3.3V Supply
128 Pin 14x20mm PQFP Package
D0+
D0-
D15+
D15-
CLK16O+
CLK16O-
DI+
DI-
HSCLKI+
HSCLKI-
Ou
tp
u
tR
eg
ist
er
Divide by
16
CLK32O+
CLK32O-
Divide by
2
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