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參數(shù)資料
| 型號(hào)： | SC488MLTRT |
| 廠商： | Semtech Corporation |
| 英文描述： | Complete DDR1/2/3 Memory Power Supply |
| 中文描述： | 完全DDR1/2/3內(nèi)存供電 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 818K |
| 代理商： | SC488MLTRT |
13
2006 Semtech Corp.
www.semtech.com
SC488
POWER MANAGEMENT
Application Information (Cont.)
Dropout Performance
The output voltage adjust range for continuous-conduction
operation is limited by the
fi
xed 400nS (typical) Minimum
Off-time One-shot. For best dropout performance, use
the slowest on-time setting of 200KHz. When working
with low input voltages, the duty-factor limit must be
calculated using worst-case values for on and off times.
The IC dutyfactorlimitation is given by:
(MAX)
TOFF
(MIN)
TON
(MIN)
TON
DUTY
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
SC488 System DC Accuracy (VDDQ Controller)
Three IC parameters affect VDDQ accuracy: the internal
1.5V reference, the error comparator offset voltage, and
the switching frequency variation with line and load.
The internal 1.5%, 1.5V reference contains two error
components, a 0.5% DC error and a 0.5% supply and tem-
perature error. The error comparator offset is trimmed so
that it trips when the feedback pin is nominally 1.5 volts
+/-1.5% at room temperature. The comparator offset trim
compensates for any DC error in the reference. Thus, the
percentage error is the sum of the reference variation
over supply and temperature and the offset in the error
comparator, or 2.0% total.
The on-time pulse in the SC488 is calculated to give a
pseudo-
fi
xed frequency. Nevertheless, some frequency
variation with line and load can be expected. This varia-
tion changes the output ripple voltage. Because constant
on-time converters regulate to the valley of the output
ripple, of the output ripple appears as a DC regulation
error. For example, If the output ripple is 50mV with VIN =
6 volts, then the measured DC output will be 25mV above
the comparator trip point. If the ripple increases to 80mV
with VIN = 25 volts, then the measured DC output will be
40mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
To compensate for valley regulation it is often desirable
to use passive droop. Take the feedback directly from the
output side of the inductor, incorporating a small amount
of trace resistance between the inductor and output ca-
pacitor. This trace resistance should be optimized so that
at full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced.
Board components and layout also in
fl
uence DC accuracy.
The use of 1% feedback resistors contributes additional
error. If tighter DC accuracy is required use 0.1% feedback
resistor.
The output inductor value may change with current. This
will change the output ripple and thus the DC output volt-
age (it will not change the frequency).
Switching frequency variation with load can be minimized
by choosing lower RDS
MOSFETs. High RDS
MOSFETS
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage. This inherent droop should be
considered when deciding if passive droop is required, or
if passive droop is desired in order to further reduce the
output capacitance.
Output DC Accuracy (VTT Output)
The VTT accuracy compared to VDDQ is determined by two
parameters: the REF output accuracy, and the VTT output
accuracy with respect to REF. The REF output is generated
internally from the VDDQS (sense input), and tracks VDDQS
with 2% accuracy. This REF output becomes the reference
for the VTT regulator. The VTT regulator then tracks REF
within +/-40mV (typically zero). The total VTT/VDDQ track-
ing accuracy is then:
40mV
0.02
2
VDDQS
error
VTT
r
r
x
DDR Reference Buffer
The reference buffer is capable of sourcing 10mA. The
reference buffer has a class A output stage and therefore
will not sink signi
fi
cant current; there is an internal 50 k
Ω
(typical) pulldown to ground. If higher current sinking is
required, an external pulldown resistor should be added.
Make sure that the ground side of this pulldown is tied to
the VTT ground plane near the PGND2 pin.
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