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15
2006 Semtech Corp.
www.semtech.com
SC486
POWER MANAGEMENT
Design Procedure - VDDQ Controller
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure an 8A VDDQ output
being used to power VTT at +/-2A for a total IDDQ of
10A will be designed.
The maximum input voltage (V
) is determined by
the highest AC adaptor voltage. The minimum input
voltage (V
) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
purposes of this design example we will use a V
BAT
range
of 9V to 19.2V.
Four parameters are needed for the output:
1) nominal output voltage, V
(for DDR2 this is 1.8V)
2) static (or DC) tolerance, TOL
ST
(we will use +/-4% for
this design )
3) transient tolerance, TOL
and size of transient (we will
use +/-100mV for this design).
4) maximum output current, I
OUT
(we are designing for
10A)
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN
2
. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. The default R
value of 715k
is
suggested as a starting point, but it is not set in stone.
The first thing to do is to calculate the on-time, t
, at
V
BAT(MIN)
and V
BAT(MAX)
, since this depends only upon V
BAT
,
V
OUT
tON
.
(
)
s
10
50
V
V
10
37
R
10
3
t
9
)
MIN
(
BAT
OUT
3
tON
12
)
MIN
(
VBAT
_
ON
+
+
=
and
(
)
s
10
50
V
V
10
37
R
10
3
t
9
)
MAX
(
BAT
OUT
3
tON
12
)
MAX
(
VBAT
_
ON
+
+
=
From these values of t
we can calculate the nominal
switching frequency as follows:
(
)
Hz
t
V
V
f
)
MIN
(
VBAT
_
ON
)
MIN
(
BAT
OUT
)
MIN
(
VBAT
_
SW
=
and
(
)
Hz
t
V
V
f
)
MAX
(
VBAT
_
ON
)
MAX
(
BAT
OUT
)
MAX
(
VBAT
_
SW
=
t
ON
is generated by a one-shot comparator that samples
V
via R
, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to V
. The
equations above reflect this along with any internal
components or delays that influence t
ON
. For our DDR2
VDDQ example we select R
tON
= 715k
:
t
ON_VBAT(MIN)
= 546ns and t
ON_VBAT(MAX)
= 283ns
f
SW_VBAT(MIN)
= 366kHz and f
SW_VBAT(MAX)
= 332kHz
Now that we know t
we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of I
OUT
which will give us a starting place.
(
)
(
5
)
H
I
t
V
V
L
OUT
)
MIN
(
VBAT
_
ON
OUT
)
MIN
(
BAT
)
MIN
(
VBAT
=
and
(
)
(
5
)
H
I
t
V
V
L
OUT
)
MAX
(
VBAT
_
ON
OUT
)
MAX
(
BAT
)
MAX
(
VBAT
=
For our DDR2 VDDQ example:
L
VBAT(MIN)
= 0.8μH and L
VBAT(MAX)
= 1.0μH
We will select an inductor value of 1.5μH to reduce the
ripple current, which can be calculated as follows:
(
)
P
P
)
MIN
(
VBAT
L
_
ON
OUT
)
MIN
(
BAT
)
MIN
(
VBAT
_
RIPPLE
I
A
t
V
V
=
and
(
)
P
P
)
MAX
(
VBAT
L
_
ON
OUT
)
MAX
(
BAT
)
MAX
(
VBAT
_
RIPPLE
I
A
t
V
V
=