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參數(shù)資料
| 型號： | SC4624SETRT |
| 廠商： | Semtech Corporation |
| 英文描述： | Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator |
| 中文描述： | 低輸入電壓，高效率及4A集成FET的同步降壓直流/直流穩(wěn)壓器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 738K |
| 代理商： | SC4624SETRT |
14
2007 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Operation
Application Information (Cont.)
SC4624
SC4624 regulates the inductor current to a new value dur-
ing a load transient, the output capacitor delivers all the
additional current needed by the load.
The ESR and ESL of the output capacitor, the loop para-
sitic inductance between the output capacitor and the
load combined with inductor ripple current are all major
contributors to the output voltage ripple.
Input Capacitor Selection
The input capacitor selection is based on its ripple cur-
rent level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by the
switching actions. For the continuous conduction mode,
the RMS value of the input capacitor can be calculated
from:
,1
IN
9
9
9
9
,
,
287
,1
287
20$;
506
&,1
u
u
This current gives the capacitor’s power loss as follows:
(65
&,1
506
&,1
&,1
5
,
3
u
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduces the overall convert-
er efficiency. The input ripple voltage mainly depends on
the input capacitor’s ESR and its capacitance for a given
load, input voltage and output voltage. Assuming that the
input current of the converter is constant, the required
input capacitance for a given voltage ripple can be calcu-
lated by:
(65
&,1
20$;
,
6
20$;
,1
5
,
'9
I
'
u
'
,
&
u
u
u
where
D = V
/V
, duty ratio.
D
V
I
= the given input voltage ripple.
Loop Compensation Design
For a DC/DC converter, it is usually required that the con-
verter has a loop gain of a high cross-over frequency for
fast load response, high DC and low frequency gain for low
steady state error, and enough phase margin for its oper-
ating stability. Often one can not have all these properties
at the same time. The purpose of the loop compensation
is to arrange the poles and zeros of the compensation
network to meet the requirements for a specific applica
-
tion.
The SC4624 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and FB pin, GND, and the output as shown in Figure
17. The compensation network includes C1, C2, R1, R7,
R8 and C8. R9 is used to program the output voltage ac
-
cording to:
5
5
9
2
u
5
5
4
4
3
3
2
2
1
1
D
C
B
A
R7
R1
C4
C1
L1
R
C2
SC4624
COMP
FB
PH
R9
C8
R8
Vout
Figure 17. Compensation Network
Provides 3 Poles and 2 Zeros
For voltage mode step down applications as shown in Fig-
ure 17, the power stage transfer function is:
where
R = load resistance
R
C
= C4’s ESR.
The compensation network will have these characteris-
tics:
2
P
2
Z
s
1
P
1
Z
I
COMP
1
s
1
s
1
s
1
s
)
G
w
+
w
+
w
+
w
+
w
=
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