參數(shù)資料
型號(hào)： SC28L202
廠商： NXP Semiconductors N.V.
英文描述： Dual universal asynchronous receiver/transmitter DUART
中文描述： 雙路通用異步接收器/發(fā)送器杜阿爾特
文件頁數(shù)： 27/77頁
文件大?。?/td> 531K
代理商： SC28L202
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
21
SFSR(7:4) Reserved
SFSR(3) Status of loop back error check.
A “1” indicates a loop back error occurred, which will be entered for
interrupt arbitration.
It can be cleared by the processor by a write to this register with
D(3) equal to “1”.
SFSR(2:1)
Certification of returned data as Valid (This feature
implies the transmitted data is being returned by the remote
receiver. )
Sets automatic checking of returned data. This mode stores
transmitted data and compares it to data returned from the remote
receiver. It is used where relative short delay times are available, up
to two characters in time . This mode will totally relieve the
processor of this task where certainty of transmission and reception
is required. The transmitted data is looped back by the remote
station with a half–bit time delay. The local transmitted data is
internally sent to the local receiver for comparison. An interrupt is
generated in the case of an error (data mismatch, parity or framing).
00 = The checking is disabled
01 = Return data is clocked in on rise of TxC
10 = Return data is clocked on of rise of TxCN
00 = Reserved
SFSR(0) Reserved
TRR Test and Revision Register.
TRR
Bit 7
Bit 6:0
Test 2
Revision Code
TRR(7) Test 2 Enable
Bypass divide by 16 counter in all TxC and RxC.
TRR [6:0] – Chip Revision Code
Indicates the revision of the chip. Initial code will be
0000000
. The
revision code bits (6:0) are hard wired. The default setting of the test
bits is all zero.
STCR – Scan Test Control Register.
Addr
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
77
Memory Test
Scan Test
Iddq Test
STCR(0)
Iddq Test – Turns off all pull–up devices on the I/O pins.
SES – System Enable Status Register, A and B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Transmitter
Enabled
Receiver
Enabled
Watch Dog
Timer
Address
Recognition
Xon
Xoff
Set to 0
Set to 0
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
This register reports the enabled status of the several sub systems in the DUART. These systems are sometimes controlled by the state
machines of the receiver FIFOs.
EOS – Enhanced Operation Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
I/O Port
Operation
Reserved
Counter/Timer
0 Clock Select
Channel B
Rx/Tx
Clock
Selection
Channel A
Rx/Tx
Clock
Selection
Channel B
FIFO
Interrupt Level
Control
Channel A FIFO
Interrupt Level
Control
0 = Default
1 = Enhanced
0 = Default
1 = Enhanced
0 = Default
1 = Enhanced
0 = Default
1 = Enhanced
0 = Default
1 = Enhanced
0 = Default
1 = Enhanced
This register reports the status of the Enhanced operation in several sub systems in the DUART.
相關(guān)PDF資料
PDF描述
SC28L202A1B Dual universal asynchronous receiver/transmitter DUART
SC28L202A1D Dual universal asynchronous receiver/transmitter DUART
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC28L202A1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1D 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1DGG 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS 256B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L202A1DGG,112 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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