參數(shù)資料
型號： SC28C94
廠商： NXP Semiconductors N.V.
英文描述： Quad universal asynchronous receiver/transmitter QUART
中文描述： 四通用異步接收器/發(fā)送器夸脫
文件頁數(shù)： 13/38頁
文件大?。?/td> 230K
代理商： SC28C94
Philips Semiconductors
Product specification
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
1998 Aug 19
13
Table 4.
Register Bit Formats, Duart ab. [duplicated for Duart cd]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MR0 (Mode Register 0)
Rx Watchdog
Timer
RxINT2 bit
TxINT Control
These bits not implemented.
They should be considered Reserved.
0 = off
1 = on
These bits should normally be set to 0
x
x
x
x
MR1 (Mode Register 1)
RxRTS
Control
0 = No
1 = Yes
RxINT1 Select
Error Mode*
Parity Mode
Parity Type
Bits per Character
Normally set to 0
0 = Char
1 = Block
00 = With parity
01 = Force parity
10 = No parity
11 = Wake-up mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
Channel Mode
TxRTS
Control
CTS
Enable
Tx
Stop Bit Length*
00 = Normal
01 = Auto-echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 C = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE:
Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CSR (Clock Select Register)
Receiver Clock Select
Transmitter Clock Select
See text
See text
CR (Command Register)
Miscellaneous Commands
Disable Tx
Enable Tx
Disable Rx
Enable Rx
See text
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE:
Issuing commands contained in the upper four bits of the “Command Register” should be separated in time by at least three (3) X1
clock edges. Allow four (4) edges if the “X1 clock divide by 2” mode is used. A disabled transmitter cannot be loaded.
SR (Status Register)
Rec’d. Break
0 = No
1 = Yes
*
NOTE:
These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. Unless reset with the ‘Error
Reset’ (CR command 40) or receiver reset, these bits will remain active in the Status Register after the RxFIFO is empty. In block error mode,
block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
Framing Error
0 = No
1 = Yes
*
Parity Error
0 = No
1 = Yes
*
Overrun Error
0 = No
1 = Yes
TxEMT
0 = No
1 = Yes
TxRDY
0 = No
1 = Yes
RxFULL
0 = No
1 = Yes
RxRDY
0 = No
1 = Yes
ACR (Auxiliary Control Register)
BRG Set
Select
0 = set 1
1 = set 2
Counter/Timer
Mode and Source
Delta
I/O1b
0 = off
1 = on
Delta
I/O0b
0 = off
1 = on
Delta
I/O1a
0 = off
1 = on
Delta
I/O0a
0 = off
1 = on
See text
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