參數(shù)資料
型號(hào): SC16C754BIB80,557
廠商: NXP Semiconductors
文件頁數(shù): 8/50頁
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 80-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 595
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(12x12)
包裝: 管件
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-1207
935274939557
SC16C754BIB80
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
16 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.5.1 Interrupt mode operation
In interrupt mode (if any bit of IER[3:0] is ‘1’) the processor is informed of the status of the
receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced. Figure 9 shows interrupt mode operation.
6.5.2 Polled mode operation
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU. Figure 10 shows FIFO polled
mode operation.
Fig 9.
Interrupt mode operation
11
IIR
IER
THR
RHR
PROCESSOR
IOW / IOR
INT
002aaa230
Fig 10. FIFO polled mode operation
00
LSR
IER
THR
RHR
PROCESSOR
IOW / IOR
002aaa231
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