參數(shù)資料
型號(hào): SC16C754BIA68,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 11/50頁(yè)
文件大?。?/td> 0K
描述: IC UART QUAD 64BYTE 68PLCC
標(biāo)準(zhǔn)包裝: 18
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 935274938529
SC16C754BIA68-S
SC16C754BIA68-S-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
19 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (216
1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 13. The output frequency of the baud rate generator is 16
× the baud rate. The
formula for the divisor is given in Equation 1:
(1)
Where:
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 13 shows the internal prescaler and baud rate generator circuitry.
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least signicant and most signicant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 14 shows the crystal clock circuit reference.
Fig 13. Prescaler and baud rate generator block diagram
divisor
XTAL1 crystal input frequency
prescaler
-------------------------------------------------------------------------------------
desired baud rate
16
×
()
------------------------------------------------------------------------------------------
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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