參數(shù)資料
型號： SC16C754BIA68,518
廠商： NXP Semiconductors
文件頁數(shù)： 15/50頁
文件大?。?/td> 0K
描述： IC UART QUAD W/FIFO 68-PLCC
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標(biāo)準(zhǔn)包裝： 1
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 828 (CN2011-ZH PDF)
其它名稱： 568-2050-6
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
22 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 10 lists and describes the SC16C754B internal registers.
[1]
These registers are accessible only when LCR[7] = 0.
[2]
This bit can only be modied if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3]
The Special register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced feature register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
Table 10.
SC16C754B internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General register set[1]
0
RHR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
THR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
0
1
IER
0/CTS
interrupt
enable[2]
0/RTS
interrupt
enable[2]
0/X Sleep
mode[2]
modem
status
interrupt
receive
line status
interrupt
THR
empty
interrupt
RX data
available
interrupt
R/W
0
1
0
FCR
RX
trigger
level
(MSB)
RX trigger
level (LSB)
0/TX
trigger
level
0/TX
trigger
level
(LSB)[2]
DMA
mode
select
TX FIFO
reset
RX FIFO
reset
FIFO
enable
W
0
1
0
IIR
FCR[0]
0/CTS,
RTS
0/Xoff
interrupt
priority
bit 2
interrupt
priority
bit 1
interrupt
priority
bit 0
interrupt
status
R
0
1
LCR
DLAB
break
control bit
set parity
parity type
select
parity
enable
number of
stop bits
word
length
bit 1
word
length
bit 0
R/W
1
0
MCR
1
× or
1
× /4
clock[2]
TCR and
TLR
enable[2]
0/Xon Any
0/enable
loopback
IRQ
enable
OP
FIFO
ready
enable
RTS
DTR
R/W
1
0
1
LSR
0/error in
RX FIFO
THR and
TSR empty
THR
empty
break
interrupt
framing
error
parity error overrun
error
data in
receiver
R
1
0
MSR
CD
RI
DSR
CTS
CD
RI
DSR
CTS
R
1
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
TLR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
FIFO
Rdy
RX FIFO
D status
RX FIFO
C status
RX FIFO
B status
RX FIFO
A status
TX FIFO
D status
TX FIFO
C status
TX FIFO
B status
TX FIFO
A status
R
Special register set[3]
0
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
1
DLM
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Enhanced register set[4]
0
1
0
EFR
auto-CTS auto-RTS
special
character
detect
enable
enhanced
functions
software
ow
control
bit 3
software
ow
control
bit 2
software
ow
control
bit 1
software
ow
control
bit 0
R/W
1
0
Xon1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
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