Clocked from separate On-chip Oscil" />
參數(shù)資料
型號(hào): SC16C654DBIB64,157
廠商: NXP Semiconductors
文件頁(yè)數(shù): 50/58頁(yè)
文件大?。?/td> 0K
描述: IC QUAD UART 64BYTE 64LQFP
標(biāo)準(zhǔn)包裝: 800
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤(pán)
其它名稱(chēng): 935276671157
SC16C654DBIB64
SC16C654DBIB64-ND
54
7674F–AVR–09/09
ATmega164P/324P/644P
9.2
Watchdog Timer
9.2.1
Features
Clocked from separate On-chip Oscillator
3 Operating modes
–Interrupt
– System Reset
– Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
9.2.2
Overview
ATmega164P/324P/644P has an Enhanced Watchdog Timer (WDT). The WDT is a timer count-
ing cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system
reset when the counter reaches a given time-out value. In normal operation mode, it is required
that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before
the time-out value is reached. If the system doesn't restart the counter, an interrupt or system
reset will be issued.
Figure 9-5.
Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-
tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and
changing time-out configuration is as follows:
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
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