參數(shù)資料
型號: SC16C550IB48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù): 29/52頁
文件大?。?/td> 639K
代理商: SC16C550IB48
Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
29 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C550 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Table 19:
Bit
Line Status Register bits description
…continued
Symbol
Description
Table 20:
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
Data Carrier Detect
. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.
MSR[6]
Ring Indicator
. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.
MSR[5]
Data Set Ready
. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.
MSR[4]
Clear To Send
. CTS. CTS functions as hardware flow control signal
input if it is enabled via EFR[7]. The transmit holding register flow control
is enabled/disabled by MSR[4]. Flow control (when enabled) allows
starting and stopping the transmissions based on the external modem
CTS signal. A logic 1 at the CTS pin will stop SC16C550 transmissions
as soon as current character has finished transmission. Normally
MSR[4] is the complement of the CTS input. However, in the loop-back
mode, this bit is equivalent to the RTS bit in the MCR register.
MSR[3]
DCD
[1]
Logic 0 = No DCD change (normal default condition).
Logic 1 = The DCD input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
MSR[2]
RI
[1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C550 has changed from a logic 0 to
a logic 1. A modem Status Interrupt will be generated.
6
5
4
3
2
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SC16C550IN40 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder
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