參數(shù)資料
型號: SC1452XIMSTRT
廠商: Semtech Corporation
英文描述: Dual 150mA LDO Regulator with Programmable Reset
中文描述: 雙150mA的LDO穩(wěn)壓器,具有可編程復(fù)位
文件頁數(shù): 7/15頁
文件大?。?/td> 299K
代理商: SC1452XIMSTRT
7
2006 Semtech Corp.
www.semtech.com
SC1452
POWER MANAGEMENT
Applications Information
ultra low dropout (ULDO) regulators, along with enable
controls and power-on resets (which function is usually
served by external devices), provides a very space
efficient solution for multiple supply requirements.
Theory Of Operation
The SC1452 is intended for applications where very low
dropout voltage, low supply current and low output noise
are critical. Furthermore, the SC1452, by combining two
The SC1452 contains two ULDOs, both of which are
supplied by one input supply, between IN and GND. Each
ULDO has its own active high enable pin (ENA/ENB).
Pulling this pin low causes that specific ULDO to enter a
very low power shutdown state.
Each ULDO also has its own power on reset pin (RSTA/
RSTB), which asserts low whenever the output voltage is
below the reset threshold for that output. Each reset
remains asserted low until a specific delay time after the
output rises back above the reset threshold. For output
A, this delay time is typically 50ms. Output B has a
programmable reset delay. If DLYB is grounded, the
reset delay will be controlled by an internal timer to
150ms. If a capacitor is connected between DLYB and
GND, a constant current, I
DLYB
, charges this capacitor until
the delay threshold, V
, is reached, or the internal
timer times out. See “Adjusting RSTB Delay Time”. One
advantage of on-board resets is that they remain asserted
low all the way down to V
= 0V, whereas
external devices may require pull-down resistors.
A bypass pin (BYP) is provided to decouple the bandgap
reference to reduce output noise (on both outputs) and
also to improve power supply rejection.
The SC1452 contains an internal bandgap reference
which is fed into the inverting input of two error
amplifiers, one for each output. The output voltage of
each regulator is divided down internally using a resistor
divider and compared to the bandgap voltage. The error
amplifier drives the gate of a low R
DS(ON)
P-channel MOSFET
pass device.
Each regulator has its own current limit circuitry to
ensure that the output current will not damage the
device during output short, overload or start-up. The
current limit is guaranteed to be greater than 400mA to
allow fast charging of the output capacitor and high
initial currents for DSP initialization.
The SC1452 has a fast start-up circuit to speed up the
initial charging time of the bypass capacitor to enable
the output voltage to come up quicker.
The SC1452 includes thermal shutdown circuitry to turn
off the device if T
exceeds 150°C (typical), with the
device remaining off until T
drops by 20°C (typical).
Reverse battery protection circuitry ensures that the
device cannot be damaged if the input supply is
accidentally reversed, limiting the reverse current to less
than 1.5mA.
Adjusting RSTB Delay Time
The power on reset delay for regulator B, t
, can be
reduced
externally by connecting a capacitor to the delay
time set pin DLYB. If DLYB is connected to ground, the
internally controlled delay time of 150ms (typ.) will apply.
Referring to the block diagram, as the output of regulator
B (V
) rises and reaches the reset threshold voltage
(92% V
), two things happen:
1) the internal 150ms timer starts;
2) the 3μA current source turns on, charging C
DLYB
(if
connected).
If DLYB is connected to ground, RSTB goes high 150ms
after V
crosses the threshold voltage. If a capacitor is
connected between DLYB and ground, the voltage at
DLYB can be described by the following equation:
An internal comparator compares this voltage to a 1.25V
reference, and triggers the reset high once this voltage
is reached. The delay time can be calculated by
rearranging the above equation, solving for t:
Note that the
maximum
delay time is 150ms, as RSTB
goes high when either the internal timer or externally set
timer times out, so if t
is set externally for 200ms,
the reset delay will still be 150ms. Thus for a 150ms
delay, DLYB should be grounded, and for a delay time
DLYB
6
DLYB
V
C
t
10
3
=
DLYB
6
DLYB
3
RSTB
C
667
,
416
10
25
.
C
t
=
=
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