參數(shù)資料
型號： SBDIP
廠商： Intersil Corporation
英文描述： High-Reliability CMOS 8-Bit Microprocessor
中文描述： 高可靠性的CMOS 8位微處理器
文件頁數(shù)： 1/8頁
文件大?。?/td> 44K
代理商： SBDIP
3-30
March 1997
CDP1802AC/3
High-Reliability CMOS 8-Bit Microprocessor
Features
For Use In Aerospace, Military, and Critical Industrial
Equipment
Minimum Instruction Fetch
-
Execute Time of 4.5
μ
s
(Maximum Clock Frequency of 3.6MHz) at V
DD
= 5V, T
A
= +25
o
C
Operation Over the Full Military
Temperature Range . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Any Combination of Standard RAM and ROM Up to
65,536 Bytes
8–Bit Parallel Organization With Bidirectional Data
Bus and Multiplexed Address Bus
16 x 16 Matrix of Registers for Use as Multiple Pro-
gram Counters, Data Pointers, or Data Registers
On-Chip DMA, Interrupt, and Flag Inputs
High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V
DD
Ordering Information
Description
The CDP1802A/3 High
-
Reliability LSI CMOS 8
-
bit register
oriented Central
-
Processing Unit (CPU) is designed for use
as a general purpose computing or control element in a wide
range of stored
-
program systems or products.
The CDP1802A/3 includes all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili-
tate system design.
The 1800 Series Architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can be
realized. The 1800 Series CPU also provides a synchronous
interface to memories and external controllers for I/O devices,
and minimizes the cost of interface controllers. Further, the I/O
interface is capable of supporting devices operating in polled,
interrupt
-
driven, or direct memory
-
access modes.
The CDP1802AC/3 is functionally identical to its predeces-
sor, the CDP1802. The “A” version includes some perfor-
mance enhancements and can be used as a direct
replacement in systems using the CDP1802.
This type is supplied in 40 lead dual
-
in
-
line sidebrazed
ceramic packages (D suffix).
Pinout
CDP1802AC/3 (SBDIP)
TOP VIEW
PACKAGE
TEMP. RANGE
(
o
C)
5V
-
3.2MHz
PKG
NO.
SBDIP
-55 to 125
CDP1802ACD3
D40.6
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
CLOCK
WAIT
CLEAR
Q
SC1
SC0
MRD
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
V
CC
N2
N1
N0
V
SS
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
V
DD
XTAL
DMA IN
DMA OUT
INTERRUPT
MWR
TPA
TPB
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
EF1
EF2
EF3
EF4
File Number
1441.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
[ /Title
(CDP1
802AC
/3)
/Sub-
ject
(High-
Reli-
ability
CMOS
8-Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8-bit
micro-
proces-
sors, 8
bit
micro-
proces-
sors,
periph-
erals)
/Cre-
ator ()
/DOCI
NFO
pdf-
mark
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