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參數(shù)資料
| 型號： | SAK-C164SV-2RF |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機(jī) |
| 文件頁數(shù)： | 55/65頁 |
| 文件大?。?/td> | 648K |
| 代理商： | SAK-C164SV-2RF |
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C164SV
Data Sheet
51
V1.0, 2003-04
Preliminary
Sample time and conversion time of the C164SV’s A/D Converter are programmable.
Table 14
should be used to calculate the above timings.
The limit values for
f
BC
must not be exceeded when selecting ADCTC.
Timing Example for 10-bit Conversion:
Assumptions:
f
CPU
Basic clock
f
BC
Sample time
t
S
Conversion 10-bit
t
C10
= 25 MHz (i.e.
t
CPU
= 40 ns), ADCTC = 00
B
, ADSTC = 00
B
.
=
f
CPU
/4 = 6.25 MHz, i.e.
t
BC
= 160 ns.
=
t
BC
×
8 = 1280 ns.
=
t
S
+ 40
t
BC
+ 2
t
CPU
= (1280 + 6400 + 80) ns = 7.8
μ
s.
Timing Example for 12-bit Conversion:
Assumptions:
f
CPU
Basic clock
f
BC
Sample time
t
S
Conversion 10-bit
t
C10
Conversion 12-bit
t
C12
= 20 MHz (i.e.
t
CPU
= 50 ns), ADCTC = 00
B
, ADSTC = 00
B
.
=
f
CPU
/4 = 5.0 MHz, i.e.
t
BC
= 200 ns.
=
t
BC
×
8 = 1600 ns.
=
t
S
+ 40
t
BC
+ 2
t
CPU
= (1600 + 8000 + 100) ns = 9.7
μ
s.
=
t
S
+ 46
t
BC
+ 2
t
CPU
= (1600 + 9200 + 100) ns = 10.9
μ
s.
7)
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.
V
AREF
=
V
DD
+ 0.2 V) the maximum TUE is increased to
±
3 LSB. This range is not 100% tested.
8)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
9)
Not 100% tested, guaranteed by design and characterization.
10)
During the sample time the input capacitance
C
AIN
can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
t
S
.
After the end of the sample time
t
S
, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time
t
S
depend on programming and can be taken from
Table 14
.
Table 14
ADCON.15|14
(ADCTC)
00
01
10
11
A/D Converter Computation Table
A/D Converter
Basic Clock
f
BC
f
CPU
/ 4
f
CPU
/ 2
f
CPU
/ 16
f
CPU
/ 8
ADCON.13|12
(ADSTC)
00
01
10
11
Sample time
t
S
t
BC
×
8
t
BC
×
16
t
BC
×
32
t
BC
×
64
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