參數(shù)資料
型號： SAK-C161JI-LF
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller
中文描述： 16位單片機(jī)
文件頁數(shù)： 66/89頁
文件大?。?/td> 876K
代理商： SAK-C161JI-LF
C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
62
V3.0, 2001-01
A/D Converter Characteristics
(Operating Conditions apply)
Table 13
Parameter
A/D Converter Characteristics
Symbol
Limit Values
min.
Unit Test
Condition
max.
V
DD
+ 0.1 V
V
SS
+ 0.2 V
V
AREF
6.25
40
t
BC
+
t
S
+ 2
t
CPU
3328
t
BC
±
2
t
BC
/ 60
- 0.25
t
S
/ 450
- 0.25
33
Analog reference supply
Analog reference ground
Analog input voltage range
Basic clock frequency
Conversion time
V
AREF
SR 4.0
V
AGND
SR
V
SS
- 0.1
V
AIN
SR
V
AGND
f
BC
t
C
CC
–
1)
1)
TUE is tested at
V
AREF
= 5.0 V,
V
AGND
= 0 V,
V
DD
= 4.9 V. It is guaranteed by design for all other voltages
within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.
V
AREF
=
V
DD
= +0.2 V) the maximum TUE is increased to
±
3 LSB. This range is not 100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see
I
OV
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be
±
4 LSB.
2)
V
AIN
may exceed
V
AGND
or
V
AREF
up to the absolute maximum ratings. However, the conversion result in
these cases will be X000
H
or X3FF
H
, respectively.
3)
The limit values for
f
BC
must not be exceeded when selecting the CPU frequency and the ADCTC setting.
4)
This parameter includes the sample time
t
S
, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock
t
BC
depend on programming and can be taken from
Table 14
.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
V
MHz
–
2)
0.5
3)
4)
t
CPU
= 1 /
f
CPU
5)
Calibration time after reset
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of analog
source
ADC input capacitance
t
CAL
TUE
R
AREF
SR –
CC –
CC –
–
LSB
k
1)
t
BC
in [ns]
6)7)
R
ASRC
SR
–
k
t
S
in [ns]
7)8)
C
AIN
CC –
pF
7)
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