參數(shù)資料
型號: SAFC505
廠商: SIEMENS AG
元件分類: 8位微控制器
英文描述: 8-Bit CMOS Microcontroller
中文描述: 8位CMOS微控制器
文件頁數(shù): 35/85頁
文件大小: 487K
代理商: SAFC505
C505L
Data Sheet
33
06.99
Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.
In compare mode 1 (see
Figure 14
) the port circuit consists of two separate latches. One latch
(which acts as a “shadow latch”) can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.
Figure 14
Compare Function in Compare Mode 1
Timer 2 Capture Modes
Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the
current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this
function.
In mode 0, the external event causing a capture is:
– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
– for the CRC register:
a positive or negative transition at the corresponding pin, depending
on the status of the bit I3FR in SFR T2CON.
In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2
contents will be latched into the appropriate capture register in the cycle following the write
instruction. In this mode no interrupt request will be generated.
MCS03856
Latch
Port
Q
Q
CLK
D
Read Pin
DD
V
D
CLK
Q
Shadow
Latch
Read Latch
Port Circuit
Internal
Bus
Latch
Write to
Compare Reg.
Compare Register
Circuit
Comparator
Timer Register
Timer Circuit
Compare
Match
Pin
Port
16 Bit
16 Bit
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