參數(shù)資料
型號(hào)： SAFC163-L
廠商： SIEMENS AG
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:37; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-35 RoHS Compliant: No
中文描述： 16位CMOS單片機(jī)
文件頁(yè)數(shù)： 37/68頁(yè)
文件大?。?/td> 625K
代理商： SAFC163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
35
1998-08
C163-L
Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during reset the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
CPU
is half the frequency of f
OSC
and the high and low time of f
CPU
(ie. the duration
of an individual TCL) is defined by the period of the input clock f
OSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the
period of f
OSC
for any TCL.
Direct Drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is disabled
and the CPU clock is directly driven from the internal oscillator with the input clock signal.
The frequency of f
CPU
directly follows the frequency of f
OSC
so the high and low time of f
CPU
(ie. the
duration of an individual TCL) is defined by the duty cycle of the input clock f
OSC
.
The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:
TCL
min
= 1/f
OSC
* DC
min
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of f
OSC
is compensated so the
duration of 2TCL is always 1/f
OSC
. The minimum value TCL
min
therefore has to be used only once
for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula 2TCL = 1/f
OSC
.
Note:
The address float timings in Multiplexed bus mode (t
11
and t
45
) use the maximum duration of
TCL (TCL
max
= 1/f
OSC
* DC
max
) instead of TCL
min
.
1) The external clock input range refers to a CPU clock range of 10...25 MHz.
2) The maximum frequency depends on the duty cycle of the external clock signal.
Direct drive is also selected instead of PLL operation if pin OWE = ’0’ in such a case.
C163-L Clock Generation Modes
P0.15-13
(P0H.7-5)
CPU Frequency
f
CPU
= f
OSC
* F
f
OSC
* 4
f
OSC
* 3
f
OSC
* 2
f
OSC
* 5
f
OSC
* 1
f
OSC
* 1.5
f
OSC
/ 2
f
OSC
* 2.5
External Clock Input
Range
1)
Notes
1
1
1
2.5 to 6.25 MHz
Default configuration
1
1
0
3.33 to 8.33 MHz
1
0
1
5 to 12.5 MHz
1
0
0
2 to 5 MHz
0
1
1
1 to 25 MHz
Direct drive
2)
0
1
0
6.66 to 16.6 MHz
0
0
1
2 to 50 MHz
CPU clock via prescaler
0
0
0
4 to 10 MHz
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